Public/LMK04828_Config_Cal
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6 Commits
0.0.1 ... main

Author SHA1 Message Date
Tifer King
e38fc7e039 Add IW-RFSOC-2T2R external preset 2025-04-25 16:40:51 +08:00
Tifer King
eeef70cd7a Modify default preset 2025-04-25 05:35:12 +08:00
Tifer King
203cca184c Fix some bugs 2025-04-25 05:33:36 +08:00
Tifer King
ee218d73f6 Add IW-RFSOC-2T2R preset 2025-01-20 03:19:20 +08:00
Tifer King
afa9e1712d Set default channel configuration 2025-01-18 02:40:25 +08:00
Tifer King
8f2f72188b Add preset configuration 2025-01-18 02:36:33 +08:00
4 changed files with 481 additions and 208 deletions
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314
LMK_ClockTree.c
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@ -7,31 +7,19 @@
#include "LMK_ClockTree.h" #include "LMK_ClockTree.h"
__weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) __weak int LMK_CalPLL1CommonRate(LMK_Simple *SimpleConfig)
{ {
int i; SimpleConfig->Generated.PLL1CommonRate = GreatestCommonDivisor(SimpleConfig->RefClockRate, SimpleConfig->VCOXClockRate);
u64 ChMaxRate; LMK_AssertInValid(SimpleConfig->Generated.PLL1CommonRate);
u64 VCORate; return LMK_SUCCESS;
u64 PLL1CommonRate; }
__weak int LMK_CalPLL2CommonRate(LMK_Simple *SimpleConfig)
{
u8 i;
u64 PLL2CommonRate; u64 PLL2CommonRate;
u64 ChMaxRate;
u64 RootDiv; u64 RootDiv;
//u64 PLLDiv;
u8 VCOSelect;
DevConfig->InterfaceInst = SimpleConfig->InterfaceInst;
PLL1CommonRate = GreatestCommonDivisor(SimpleConfig->RefClockRate, SimpleConfig->VCOXClockRate);
/*if(PLL1CommonRate > LMK_PLL1_LFBAND)
{
PLLDiv = PLL1CommonRate / LMK_PLL1_LFBAND;
PLL1CommonRate /= PLLDiv + 1;
}*/
if(PLL1CommonRate < 1000)
{
return XST_FAILURE;
}
ChMaxRate = 0; ChMaxRate = 0;
for(i = 0; i < 7; i++) for(i = 0; i < 7; i++)
{ {
@ -47,41 +35,51 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
} }
} }
} }
LMK_AssertZero(ChMaxRate);
if(ChMaxRate == 0)
{
return XST_FAILURE;
}
if((LMK_VCO0_RATE_L / ChMaxRate) < (LMK_VCO0_RATE_H / ChMaxRate)) if((LMK_VCO0_RATE_L / ChMaxRate) < (LMK_VCO0_RATE_H / ChMaxRate))
{ {
RootDiv = (LMK_VCO0_RATE_L / ChMaxRate) + 1; RootDiv = (LMK_VCO0_RATE_L / ChMaxRate) + 1;
VCORate = RootDiv * ChMaxRate; SimpleConfig->Generated.VCORate = RootDiv * ChMaxRate;
VCOSelect = 0; SimpleConfig->Generated.VCOSelect = 0;
} }
else if((LMK_VCO1_RATE_L / ChMaxRate) < (LMK_VCO1_RATE_H / ChMaxRate)) else if((LMK_VCO1_RATE_L / ChMaxRate) < (LMK_VCO1_RATE_H / ChMaxRate))
{ {
RootDiv = (LMK_VCO1_RATE_L / ChMaxRate) + 1; RootDiv = (LMK_VCO1_RATE_L / ChMaxRate) + 1;
VCORate = RootDiv * ChMaxRate; SimpleConfig->Generated.VCORate = RootDiv * ChMaxRate;
VCOSelect = 1; SimpleConfig->Generated.VCOSelect = 1;
} }
else else
{ {
return XST_FAILURE; return LMK_FAILURE;
} }
PLL2CommonRate = GreatestCommonDivisor(SimpleConfig->Generated.VCORate / 2, SimpleConfig->VCOXClockRate);
LMK_AssertInValid(PLL2CommonRate);
SimpleConfig->Generated.PLL2CommonRate = PLL2CommonRate;
return LMK_SUCCESS;
}
PLL2CommonRate = GreatestCommonDivisor(VCORate, SimpleConfig->VCOXClockRate * 2) / 2; __weak int LMK_CalRegister(LMK_Simple *SimpleConfig)
/*if(PLL2CommonRate > LMK_PLL2_LFBAND) {
int i;
LMK_AssertZero(SimpleConfig->SYSREFRate);
LMK_AssertZero(SimpleConfig->Generated.PLL1CommonRate);
LMK_AssertZero(SimpleConfig->Generated.PLL2CommonRate);
SimpleConfig->Generated.SYSREF_DIV = SimpleConfig->Generated.VCORate / SimpleConfig->SYSREFRate;
SimpleConfig->Generated.CLKin_R = SimpleConfig->RefClockRate / SimpleConfig->Generated.PLL1CommonRate;
SimpleConfig->Generated.PLL1_N = SimpleConfig->VCOXClockRate / SimpleConfig->Generated.PLL1CommonRate;
SimpleConfig->Generated.PLL2_R = SimpleConfig->VCOXClockRate / SimpleConfig->Generated.PLL2CommonRate;
SimpleConfig->Generated.PLL2_N = SimpleConfig->Generated.VCORate / SimpleConfig->Generated.PLL2CommonRate / 2;
for(i = 0; i < 7; i++)
{ {
PLLDiv = PLL2CommonRate / LMK_PLL2_LFBAND; SimpleConfig->Generated.DCLKout_Div[i] = SimpleConfig->DClockRate[i] == 0 ? 0 : SimpleConfig->Generated.VCORate / SimpleConfig->DClockRate[i];
PLL2CommonRate /= PLLDiv + 1;
}*/
if(PLL2CommonRate < 1000)
{
return XST_FAILURE;
} }
return LMK_SUCCESS;
}
int LMK_ConfigInitRegister(LMK_Config *DevConfig)
{
int i;
// Fixed Register Set // Fixed Register Set
DevConfig->Config.Fixed_0 = 0x7F; DevConfig->Config.Fixed_0 = 0x7F;
DevConfig->Config.Fixed_1 = 0x01; DevConfig->Config.Fixed_1 = 0x01;
@ -89,20 +87,20 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.Fixed_3 = 0x02; DevConfig->Config.Fixed_3 = 0x02;
// Calculate Register Value // Calculate Register Value
DevConfig->Config.OSCout_FMT = 0x00; DevConfig->Config.OSCout_FMT = 4;
DevConfig->Config.OSCout_MUX = 0; DevConfig->Config.OSCout_MUX = 0;
DevConfig->Config.VCO_MUX = VCOSelect; DevConfig->Config.VCO_MUX = 0;
DevConfig->Config.SYSREF_MUX = 3; DevConfig->Config.SYSREF_MUX = 0;
DevConfig->Config.SYSREF_CLKin0_MUX = 0; DevConfig->Config.SYSREF_CLKin0_MUX = 0;
DevConfig->Config.SYSREF_DIVH = (VCORate / SimpleConfig->SYSREFRate) >> 8; DevConfig->Config.SYSREF_DIVH = 12;
DevConfig->Config.SYSREF_DIVL = (VCORate / SimpleConfig->SYSREFRate) & 0xFF; DevConfig->Config.SYSREF_DIVL = 0;
DevConfig->Config.SYSREF_DDLYH = 0; DevConfig->Config.SYSREF_DDLYH = 0;
DevConfig->Config.SYSREF_DDLYL = 8; DevConfig->Config.SYSREF_DDLYL = 8;
DevConfig->Config.SYSREF_PULSE_CNT = 0x03; DevConfig->Config.SYSREF_PULSE_CNT = 3;
DevConfig->Config.FB_MUX_EN = 0; DevConfig->Config.FB_MUX_EN = 0;
DevConfig->Config.FB_MUX = 0; DevConfig->Config.FB_MUX = 0;
@ -110,7 +108,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.PLL2_NCLK_MUX = 0; DevConfig->Config.PLL2_NCLK_MUX = 0;
DevConfig->Config.SYSREF_PLSR_PD = 1; DevConfig->Config.SYSREF_PLSR_PD = 1;
DevConfig->Config.SYSREF_DDLY_PD = 0; DevConfig->Config.SYSREF_DDLY_PD = 1;
DevConfig->Config.SYSREF_PD = 1; DevConfig->Config.SYSREF_PD = 1;
DevConfig->Config.SYSREF_GBL_PD = 0; DevConfig->Config.SYSREF_GBL_PD = 0;
DevConfig->Config.OSCin_PD = 0; DevConfig->Config.OSCin_PD = 0;
@ -137,33 +135,33 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.SYNC_1SHOT_EN = 0; DevConfig->Config.SYNC_1SHOT_EN = 0;
DevConfig->Config.SYSREF_CLR = 1; DevConfig->Config.SYSREF_CLR = 1;
DevConfig->Config.SYNC_DIS0 = 1; DevConfig->Config.SYNC_DIS0 = 0;
DevConfig->Config.SYNC_DIS2 = 1; DevConfig->Config.SYNC_DIS2 = 0;
DevConfig->Config.SYNC_DIS4 = 1; DevConfig->Config.SYNC_DIS4 = 0;
DevConfig->Config.SYNC_DIS6 = 1; DevConfig->Config.SYNC_DIS6 = 0;
DevConfig->Config.SYNC_DIS8 = 1; DevConfig->Config.SYNC_DIS8 = 0;
DevConfig->Config.SYNC_DIS10 = 1; DevConfig->Config.SYNC_DIS10 = 0;
DevConfig->Config.SYNC_DIS12 = 1; DevConfig->Config.SYNC_DIS12 = 0;
DevConfig->Config.SYNC_DISSYSREF = 1; DevConfig->Config.SYNC_DISSYSREF = 0;
DevConfig->Config.CLKin0_TYPE = 0; DevConfig->Config.CLKin0_TYPE = 0;
DevConfig->Config.CLKin1_TYPE = 0; DevConfig->Config.CLKin1_TYPE = 0;
DevConfig->Config.CLKin2_TYPE = 0; DevConfig->Config.CLKin2_TYPE = 0;
DevConfig->Config.CLKin0_EN = 0; DevConfig->Config.CLKin0_EN = 1;
DevConfig->Config.CLKin1_EN = 0; DevConfig->Config.CLKin1_EN = 1;
DevConfig->Config.CLKin2_EN = 0; DevConfig->Config.CLKin2_EN = 0;
DevConfig->Config.CLKin0_OUT_MUX = 3; DevConfig->Config.CLKin0_OUT_MUX = 2;
DevConfig->Config.CLKin1_OUT_MUX = 3; DevConfig->Config.CLKin1_OUT_MUX = 2;
DevConfig->Config.CLKin_SEL_MODE = 2; DevConfig->Config.CLKin_SEL_MODE = 3;
DevConfig->Config.CLKin_SEL_POL = 0; DevConfig->Config.CLKin_SEL_POL = 0;
DevConfig->Config.CLKin_SEL0_TYPE = 3; DevConfig->Config.CLKin_SEL0_TYPE = 2;
DevConfig->Config.CLKin_SEL0_MUX = 6; DevConfig->Config.CLKin_SEL0_MUX = 0;
DevConfig->Config.CLKin_SEL1_TYPE = 0; DevConfig->Config.CLKin_SEL1_TYPE = 2;
DevConfig->Config.CLKin_SEL1_MUX = 0; DevConfig->Config.CLKin_SEL1_MUX = 0;
DevConfig->Config.SDIO_RDBK_TYPE = 0; DevConfig->Config.SDIO_RDBK_TYPE = 1;
DevConfig->Config.RESET_TYPE = 2; DevConfig->Config.RESET_TYPE = 2;
DevConfig->Config.RESET_MUX = 0; DevConfig->Config.RESET_MUX = 0;
@ -182,7 +180,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.DAC_TRIP_HIGH = 0; DevConfig->Config.DAC_TRIP_HIGH = 0;
DevConfig->Config.DAC_CLK_MULT = 0; DevConfig->Config.DAC_CLK_MULT = 0;
DevConfig->Config.DAC_CLK_CNTR = 0x7F; DevConfig->Config.DAC_CLK_CNTR = 127;
DevConfig->Config.HOLDOVER_EN = 1; DevConfig->Config.HOLDOVER_EN = 1;
DevConfig->Config.HOLDOVER_HITLESS_SW = 1; DevConfig->Config.HOLDOVER_HITLESS_SW = 1;
@ -198,13 +196,13 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.CLKin0_RL = 120; DevConfig->Config.CLKin0_RL = 120;
DevConfig->Config.CLKin1_RH = 0; DevConfig->Config.CLKin1_RH = 0;
DevConfig->Config.CLKin1_RL = 150; DevConfig->Config.CLKin1_RL = 150;
DevConfig->Config.CLKin2_RH = (SimpleConfig->RefClockRate / PLL1CommonRate) >> 8; DevConfig->Config.CLKin2_RH = 0;
DevConfig->Config.CLKin2_RL = (SimpleConfig->RefClockRate / PLL1CommonRate) & 0xFF; DevConfig->Config.CLKin2_RL = 150;
DevConfig->Config.PLL1_NH = (SimpleConfig->VCOXClockRate / PLL1CommonRate) >> 8; DevConfig->Config.PLL1_NH = 0;
DevConfig->Config.PLL1_NL = ((SimpleConfig->VCOXClockRate / PLL1CommonRate) & 0xFF); DevConfig->Config.PLL1_NL = 120;
DevConfig->Config.PLL1_CP_GAIN = 15; DevConfig->Config.PLL1_CP_GAIN = 4;
DevConfig->Config.PLL1_CP_POL = 1; DevConfig->Config.PLL1_CP_POL = 1;
DevConfig->Config.PLL1_CP_TRI = 0; DevConfig->Config.PLL1_CP_TRI = 0;
DevConfig->Config.PLL1_WND_SIZE = 3; DevConfig->Config.PLL1_WND_SIZE = 3;
@ -215,25 +213,25 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.PLL1_N_DLY = 0; DevConfig->Config.PLL1_N_DLY = 0;
DevConfig->Config.PLL1_R_DLY = 0; DevConfig->Config.PLL1_R_DLY = 0;
DevConfig->Config.PLL1_LD_TYPE = 3; DevConfig->Config.PLL1_LD_TYPE = 6;
DevConfig->Config.PLL1_LD_MUX = 1; DevConfig->Config.PLL1_LD_MUX = 1;
DevConfig->Config.PLL2_RH = (SimpleConfig->VCOXClockRate / PLL2CommonRate) >> 8; DevConfig->Config.PLL2_RH = 0;
DevConfig->Config.PLL2_RL = (SimpleConfig->VCOXClockRate / PLL2CommonRate) & 0xFF; DevConfig->Config.PLL2_RL = 2;
DevConfig->Config.PLL2_REF_2X_EN = 0; DevConfig->Config.PLL2_REF_2X_EN = 1;
DevConfig->Config.PLL2_XTAL_EN = 0; DevConfig->Config.PLL2_XTAL_EN = 0;
DevConfig->Config.OSCin_FREQ = 4; DevConfig->Config.OSCin_FREQ = 7;
DevConfig->Config.PLL2_P = 2; DevConfig->Config.PLL2_P = 2;
DevConfig->Config.PLL2_N_CALH = 0; DevConfig->Config.PLL2_N_CALH = 0;
DevConfig->Config.PLL2_N_CALM = 0; DevConfig->Config.PLL2_N_CALM = 0;
DevConfig->Config.PLL2_N_CALL = 12; DevConfig->Config.PLL2_N_CALL = 12;
DevConfig->Config.PLL2_NH = ((VCORate / PLL2CommonRate / 2) >> 16) & 0xFF; DevConfig->Config.PLL2_NH = 0;
DevConfig->Config.PLL2_FCAL_DIS = 0; DevConfig->Config.PLL2_FCAL_DIS = 0;
DevConfig->Config.PLL2_NM = ((VCORate / PLL2CommonRate / 2) >> 8) & 0xFF; DevConfig->Config.PLL2_NM = 0;
DevConfig->Config.PLL2_NL = (VCORate / PLL2CommonRate / 2) & 0xFF; DevConfig->Config.PLL2_NL = 12;
DevConfig->Config.PLL2_CP_TRI = 0; DevConfig->Config.PLL2_CP_TRI = 0;
DevConfig->Config.PLL2_CP_POL = 0; DevConfig->Config.PLL2_CP_POL = 0;
@ -241,7 +239,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.PLL2_WND_SIZE = 2; DevConfig->Config.PLL2_WND_SIZE = 2;
DevConfig->Config.PLL2_DLD_CNTH = 32; DevConfig->Config.PLL2_DLD_CNTH = 32;
DevConfig->Config.SYSREF_REQ_EN = 1; DevConfig->Config.SYSREF_REQ_EN = 0;
DevConfig->Config.PLL2_DLD_CNTL = 0; DevConfig->Config.PLL2_DLD_CNTL = 0;
DevConfig->Config.PLL2_LF_R3 = 0; DevConfig->Config.PLL2_LF_R3 = 0;
@ -249,7 +247,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.PLL2_LF_C3 = 0; DevConfig->Config.PLL2_LF_C3 = 0;
DevConfig->Config.PLL2_LF_C4 = 0; DevConfig->Config.PLL2_LF_C4 = 0;
DevConfig->Config.PLL2_LD_TYPE = 3; DevConfig->Config.PLL2_LD_TYPE = 6;
DevConfig->Config.PLL2_LD_MUX = 2; DevConfig->Config.PLL2_LD_MUX = 2;
DevConfig->Config.PLL2_PD = 0; DevConfig->Config.PLL2_PD = 0;
@ -258,42 +256,6 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.VCO1_DIV = 0; DevConfig->Config.VCO1_DIV = 0;
for(i = 0; i < 7; i++) for(i = 0; i < 7; i++)
{
if(VCORate / SimpleConfig->DClockRate[i] != 0)
{
DevConfig->Config.Clock[i].DCLKout_Div = VCORate / SimpleConfig->DClockRate[i];
DevConfig->Config.Clock[i].CLKout_IDL = 0;
DevConfig->Config.Clock[i].CLKout_ODL = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 2;
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 2;
DevConfig->Config.Clock[i].DCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_ALDY = 0;
DevConfig->Config.Clock[i].SDCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLKout_DDLY = 0;
DevConfig->Config.Clock[i].SDCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLK_ADLY = 0;
DevConfig->Config.Clock[i].SDCLKout_ADLY_EN = 0;
DevConfig->Config.Clock[i].SDCLKout_PD = 0;
DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0;
DevConfig->Config.Clock[i].CLKout_PD = 0;
DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_HSg_PD = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 0;
DevConfig->Config.Clock[i].DCLKout_FMT = 1;
DevConfig->Config.Clock[i].DCLKout_POL = 0;
DevConfig->Config.Clock[i].SDCLKout_FMT = 1;
DevConfig->Config.Clock[i].SDCLKout_POL = 0;
}
else
{ {
DevConfig->Config.Clock[i].DCLKout_Div = 0; DevConfig->Config.Clock[i].DCLKout_Div = 0;
DevConfig->Config.Clock[i].CLKout_IDL = 0; DevConfig->Config.Clock[i].CLKout_IDL = 0;
@ -302,13 +264,13 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 5; DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 5;
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 5; DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 5;
DevConfig->Config.Clock[i].DCLKout_MUX = 1; DevConfig->Config.Clock[i].DCLKout_MUX = 0;
DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1; DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 0;
DevConfig->Config.Clock[i].DCLKout_ALDY = 0; DevConfig->Config.Clock[i].DCLKout_ALDY = 0;
DevConfig->Config.Clock[i].SDCLKout_HS = 0; DevConfig->Config.Clock[i].SDCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLKout_DDLY = 0; DevConfig->Config.Clock[i].SDCLKout_DDLY = 0;
DevConfig->Config.Clock[i].SDCLKout_MUX = 1; DevConfig->Config.Clock[i].SDCLKout_MUX = 0;
DevConfig->Config.Clock[i].DCLKout_HS = 0; DevConfig->Config.Clock[i].DCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLK_ADLY = 0; DevConfig->Config.Clock[i].SDCLK_ADLY = 0;
@ -320,25 +282,50 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1; DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1; DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_HSg_PD = 1; DevConfig->Config.Clock[i].DCLKout_HSg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 1; DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 0;
DevConfig->Config.Clock[i].DCLKout_FMT = 0; DevConfig->Config.Clock[i].DCLKout_FMT = 0;
DevConfig->Config.Clock[i].DCLKout_POL = 0; DevConfig->Config.Clock[i].DCLKout_POL = 0;
DevConfig->Config.Clock[i].SDCLKout_FMT = 0; DevConfig->Config.Clock[i].SDCLKout_FMT = 0;
DevConfig->Config.Clock[i].SDCLKout_POL = 0; DevConfig->Config.Clock[i].SDCLKout_POL = 0;
} }
return LMK_SUCCESS;
}
LMK_ConfigCustomize(DevConfig);
return XST_SUCCESS;
} }
__weak int LMK_ConfigCustomize(LMK_Config *DevConfig) __weak int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
{ {
UNUSED(DevConfig); UNUSED(DevConfig);
return XST_FAILURE; UNUSED(SimpleConfig);
return LMK_SUCCESS;
}
__weak int LMK_ConfigPreset(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
{
UNUSED(DevConfig);
UNUSED(SimpleConfig);
return LMK_SUCCESS;
}
__weak int LMK_ConfigCustomize(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
{
UNUSED(DevConfig);
UNUSED(SimpleConfig);
return LMK_SUCCESS;
}
__weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
{
LMK_AssertZero(SimpleConfig->InterfaceInst);
LMK_AssertFailure(LMK_CalPLL1CommonRate(SimpleConfig));
LMK_AssertFailure(LMK_CalPLL2CommonRate(SimpleConfig));
LMK_AssertFailure(LMK_CalRegister(SimpleConfig));
LMK_AssertFailure(LMK_ConfigInitRegister(DevConfig));
LMK_AssertFailure(LMK_ConfigSetRegister(DevConfig, SimpleConfig));
LMK_AssertFailure(LMK_ConfigPreset(DevConfig, SimpleConfig));
LMK_AssertFailure(LMK_ConfigCustomize(DevConfig, SimpleConfig));
DevConfig->InterfaceInst = SimpleConfig->InterfaceInst;
return LMK_SUCCESS;
} }
int LMK_Init(LMK_Config *DevConfig) int LMK_Init(LMK_Config *DevConfig)
@ -347,25 +334,17 @@ int LMK_Init(LMK_Config *DevConfig)
uint8_t tmp; uint8_t tmp;
uint8_t ld1, ld2; uint8_t ld1, ld2;
//Unlock SPI Register //Unlock SPI Register
//LMK_WriteReg(DevConfig, 0x1FFD, 0);
//LMK_WriteReg(DevConfig, 0x1FFE, 0);
//LMK_WriteReg(DevConfig, 0x1FFF, 83);
LMK_RegUnlock(DevConfig); LMK_RegUnlock(DevConfig);
//Reset Register //Reset Register
LMK_WriteReg(DevConfig, 0x000, 0x80); LMK_WriteReg(DevConfig, 0x000, 0x80);
//4-wire SPI //Enable 4-wire SPI
LMK_WriteReg(DevConfig, 0x000, 0x10); LMK_WriteReg(DevConfig, 0x000, 0x10);
//Reserved Register
//LMK_WriteReg(DevConfig, 0x145, 0x7F);
//LMK_WriteReg(DevConfig, 0x171, 0xAA);
//LMK_WriteReg(DevConfig, 0x172, 0x02);
//LMK_WriteReg(DevConfig, 0x17C, 21);
//LMK_WriteReg(DevConfig, 0x17D, 51);
//Sequence Program //Sequence Program
LMK_WriteReg(DevConfig, 0x17C, 21);
LMK_WriteReg(DevConfig, 0x17D, 51);
for(i = 0; i < sizeof(DevConfig->Config); i++) for(i = 0; i < sizeof(DevConfig->Config); i++)
{ {
LMK_WriteReg(DevConfig, 0x100 + i, ((u8*)(&DevConfig->Config))[i]); LMK_WriteReg(DevConfig, 0x100 + i, ((u8*)(&DevConfig->Config))[i]);
@ -391,17 +370,12 @@ int LMK_Init(LMK_Config *DevConfig)
LMK_WriteReg(DevConfig, 0x139, ((u8*)(&DevConfig->Config))[0x039]); //SYSREF_MUX*/ LMK_WriteReg(DevConfig, 0x139, ((u8*)(&DevConfig->Config))[0x039]); //SYSREF_MUX*/
LMK_RegLock(DevConfig); LMK_RegLock(DevConfig);
return LMK_SUCCESS;
//Lock SPI Register
//LMK_WriteReg(DevConfig, 0x1FFD, 255);
//LMK_WriteReg(DevConfig, 0x1FFE, 255);
//LMK_WriteReg(DevConfig, 0x1FFF, 255);
return XST_SUCCESS;
} }
int LMK_StatusRead(LMK_Config *DevConfig) __weak int LMK_StatusRead(LMK_Config *DevConfig)
{ {
return XST_SUCCESS; return LMK_SUCCESS;
} }
int LMK_RegLock(LMK_Config *DevConfig) int LMK_RegLock(LMK_Config *DevConfig)
@ -409,7 +383,7 @@ int LMK_RegLock(LMK_Config *DevConfig)
LMK_WriteReg(DevConfig, 0x1FFD, 255); LMK_WriteReg(DevConfig, 0x1FFD, 255);
LMK_WriteReg(DevConfig, 0x1FFE, 255); LMK_WriteReg(DevConfig, 0x1FFE, 255);
LMK_WriteReg(DevConfig, 0x1FFF, 255); LMK_WriteReg(DevConfig, 0x1FFF, 255);
return XST_SUCCESS; return LMK_SUCCESS;
} }
int LMK_RegUnlock(LMK_Config *DevConfig) int LMK_RegUnlock(LMK_Config *DevConfig)
@ -417,39 +391,21 @@ int LMK_RegUnlock(LMK_Config *DevConfig)
LMK_WriteReg(DevConfig, 0x1FFD, 0); LMK_WriteReg(DevConfig, 0x1FFD, 0);
LMK_WriteReg(DevConfig, 0x1FFE, 0); LMK_WriteReg(DevConfig, 0x1FFE, 0);
LMK_WriteReg(DevConfig, 0x1FFF, 83); LMK_WriteReg(DevConfig, 0x1FFF, 83);
return XST_SUCCESS; return LMK_SUCCESS;
} }
#include "xspips.h" __weak int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value)
int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value)
{ {
u8 buf[3]; UNUSED(DevConfig);
UNUSED(RegisterAddress);
buf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F); UNUSED(Value);
buf[1] = RegisterAddress & 0xFF; return LMK_SUCCESS;
buf[2] = Value;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, NULL, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
return XST_SUCCESS;
} }
int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value) __weak int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value)
{ {
u8 buf[3]; UNUSED(DevConfig);
UNUSED(RegisterAddress);
buf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F); UNUSED(Value);
buf[1] = RegisterAddress & 0xFF; return LMK_SUCCESS;
buf[2] = 0;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, buf, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
*Value = buf[2];
return XST_SUCCESS;
} }

51
LMK_ClockTree.h
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@ -14,6 +14,29 @@
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#define UNUSED(x) (void)x #define UNUSED(x) (void)x
#define LMK_SUCCESS 0
#define LMK_FAILURE 1
#define LMK_AssertInValid(Expression) \
{ \
if ((Expression) < 1000) { \
return LMK_FAILURE; \
} \
}
#define LMK_AssertZero(Expression) \
{ \
if ((Expression) == 0) { \
return LMK_FAILURE; \
} \
}
#define LMK_AssertFailure(Expression) \
{ \
if ((Expression) != LMK_SUCCESS) { \
return LMK_FAILURE; \
} \
}
#define LMK_VCO0_RATE_L 2370000000 #define LMK_VCO0_RATE_L 2370000000
#define LMK_VCO0_RATE_H 2630000000 #define LMK_VCO0_RATE_H 2630000000
@ -270,6 +293,20 @@ typedef struct LMK_Config_Type
LMK_ReadBack Status; LMK_ReadBack Status;
} LMK_Config; } LMK_Config;
typedef struct LMK_Config_Generated_Type
{
u64 PLL1CommonRate;
u64 PLL2CommonRate;
u64 VCORate;
u16 SYSREF_DIV;
u16 CLKin_R;
u16 PLL1_N;
u16 PLL2_R;
u32 PLL2_N;
u8 VCOSelect;
u8 DCLKout_Div[7];
} LMK_Generated;
typedef struct LMK_Config_Simple_Type typedef struct LMK_Config_Simple_Type
{ {
void *InterfaceInst; void *InterfaceInst;
@ -278,19 +315,25 @@ typedef struct LMK_Config_Simple_Type
u64 VCOXClockRate; u64 VCOXClockRate;
u64 DClockRate[7]; u64 DClockRate[7];
u64 SYSREFRate; u64 SYSREFRate;
//Generated config
LMK_Generated Generated;
} LMK_Simple; } LMK_Simple;
int LMK_CalPLL1CommonRate(LMK_Simple *SimpleConfig);
int LMK_CalPLL2CommonRate(LMK_Simple *SimpleConfig);
int LMK_CalRegister(LMK_Simple *SimpleConfig);
int LMK_ConfigInitRegister(LMK_Config *DevConfig);
int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
int LMK_ConfigPreset(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
int LMK_ConfigCustomize(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig); int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
int LMK_ConfigCustomize(LMK_Config *DevConfig);
int LMK_Init(LMK_Config *DevConfig); int LMK_Init(LMK_Config *DevConfig);
int LMK_StatusRead(LMK_Config *DevConfig); int LMK_StatusRead(LMK_Config *DevConfig);
int LMK_RegLock(LMK_Config *DevConfig); int LMK_RegLock(LMK_Config *DevConfig);
int LMK_RegUnlock(LMK_Config *DevConfig); int LMK_RegUnlock(LMK_Config *DevConfig);
int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value); int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value);
int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value); int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value);
#endif /* SRC_LMK_CLOCKTREE_H_ */ #endif /* SRC_LMK_CLOCKTREE_H_ */

255
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@ -0,0 +1,255 @@
/*
* LMK_Preset.c
*
* Created on: 2025.01.16
* Author: TiferKing
*/
#include "LMK_Preset.h"
#ifdef LMK_PRESET_NONE
#endif //LMK_PRESET_NONE
#ifdef LMK_PRESET_IW_RFSOC_2T2R_INTERNAL
#include "xspips.h"
int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
{
int i;
// Calculate Register Value
DevConfig->Config.OSCout_FMT = 0;
DevConfig->Config.OSCout_MUX = 1;
DevConfig->Config.VCO_MUX = SimpleConfig->Generated.VCOSelect;
DevConfig->Config.SYSREF_MUX = 3;
DevConfig->Config.SYSREF_DIVH = SimpleConfig->Generated.SYSREF_DIV >> 8;
DevConfig->Config.SYSREF_DIVL = SimpleConfig->Generated.SYSREF_DIV & 0xFF;
DevConfig->Config.PLL1_NCLK_MUX = 0;
DevConfig->Config.PLL2_NCLK_MUX = 0;
DevConfig->Config.SYNC_DIS0 = 1;
DevConfig->Config.SYNC_DIS2 = 1;
DevConfig->Config.SYNC_DIS4 = 1;
DevConfig->Config.SYNC_DIS6 = 1;
DevConfig->Config.SYNC_DIS8 = 1;
DevConfig->Config.SYNC_DIS10 = 1;
DevConfig->Config.SYNC_DIS12 = 1;
DevConfig->Config.SYNC_DISSYSREF = 1;
DevConfig->Config.CLKin0_TYPE = 0;
DevConfig->Config.CLKin1_TYPE = 0;
DevConfig->Config.CLKin2_TYPE = 0;
DevConfig->Config.CLKin0_EN = 0;
DevConfig->Config.CLKin1_EN = 0;
DevConfig->Config.CLKin2_EN = 0;
DevConfig->Config.CLKin0_OUT_MUX = 3;
// Set CLKin with SPI, release CLKin_SEL0 PIN.
DevConfig->Config.CLKin1_OUT_MUX = 3;
DevConfig->Config.CLKin_SEL_MODE = 2;
// Set CLKin_SEL0 as SPI readback.
DevConfig->Config.CLKin_SEL0_TYPE = 3;
DevConfig->Config.CLKin_SEL0_MUX = 6;
DevConfig->Config.CLKin_SEL1_TYPE = 0;
DevConfig->Config.CLKin_SEL1_MUX = 0;
DevConfig->Config.SDIO_RDBK_TYPE = 0;
DevConfig->Config.RESET_TYPE = 2;
DevConfig->Config.RESET_MUX = 0;
DevConfig->Config.CLKin2_RH = SimpleConfig->Generated.CLKin_R >> 8;
DevConfig->Config.CLKin2_RL = SimpleConfig->Generated.CLKin_R & 0xFF;
DevConfig->Config.PLL1_NH = SimpleConfig->Generated.PLL1_N >> 8;
DevConfig->Config.PLL1_NL = SimpleConfig->Generated.PLL1_N & 0xFF;
DevConfig->Config.PLL1_LD_TYPE = 3;
DevConfig->Config.PLL1_LD_MUX = 1;
DevConfig->Config.PLL2_RH = SimpleConfig->Generated.PLL2_R >> 8;
DevConfig->Config.PLL2_RL = SimpleConfig->Generated.PLL2_R & 0xFF;
DevConfig->Config.PLL2_REF_2X_EN = 0;
DevConfig->Config.PLL2_XTAL_EN = 0;
DevConfig->Config.OSCin_FREQ = 4;
DevConfig->Config.PLL2_P = 2;
DevConfig->Config.PLL2_NH = (SimpleConfig->Generated.PLL2_N >> 16) & 0xFF;
DevConfig->Config.PLL2_FCAL_DIS = 0;
DevConfig->Config.PLL2_NM = (SimpleConfig->Generated.PLL2_N >> 8) & 0xFF;
DevConfig->Config.PLL2_NL = SimpleConfig->Generated.PLL2_N & 0xFF;
DevConfig->Config.PLL2_LD_TYPE = 3;
DevConfig->Config.PLL2_LD_MUX = 2;
for(i = 0; i < 7; i++)
{
if(SimpleConfig->Generated.DCLKout_Div[i] != 0)
{
DevConfig->Config.Clock[i].DCLKout_Div = SimpleConfig->Generated.DCLKout_Div[i];
DevConfig->Config.Clock[i].DCLKout_MUX = 1;
DevConfig->Config.Clock[i].SDCLKout_HS = 1;
DevConfig->Config.Clock[i].SDCLKout_DDLY = 0;
DevConfig->Config.Clock[i].SDCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLKout_PD = 0;
DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0;
DevConfig->Config.Clock[i].CLKout_PD = 0;
DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_HSg_PD = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_FMT = 1;
DevConfig->Config.Clock[i].DCLKout_POL = 0;
DevConfig->Config.Clock[i].SDCLKout_FMT = 1;
DevConfig->Config.Clock[i].SDCLKout_POL = 0;
}
}
return LMK_SUCCESS;
}
int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value)
{
u8 writebuf[3];
writebuf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F);
writebuf[1] = RegisterAddress & 0xFF;
writebuf[2] = Value;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, writebuf, NULL, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
return LMK_SUCCESS;
}
int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value)
{
u8 readbuf[3];
readbuf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F);
readbuf[1] = RegisterAddress & 0xFF;
readbuf[2] = 0;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, readbuf, readbuf, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
*Value = readbuf[2];
return LMK_SUCCESS;
}
#endif //LMK_PRESET_IW_RFSOC_2T2R_INTERNAL
#ifdef LMK_PRESET_IW_RFSOC_2T2R_EXTERNAL
#include "xspips.h"
int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
{
int i;
// Calculate Register Value
DevConfig->Config.OSCout_FMT = 0;
DevConfig->Config.OSCout_MUX = 1;
DevConfig->Config.VCO_MUX = SimpleConfig->Generated.VCOSelect;
DevConfig->Config.SYSREF_MUX = 3;
DevConfig->Config.SYSREF_DIVH = SimpleConfig->Generated.SYSREF_DIV >> 8;
DevConfig->Config.SYSREF_DIVL = SimpleConfig->Generated.SYSREF_DIV & 0xFF;
DevConfig->Config.PLL1_NCLK_MUX = 0;
DevConfig->Config.PLL2_NCLK_MUX = 0;
DevConfig->Config.SYNC_DIS0 = 1;
DevConfig->Config.SYNC_DIS2 = 1;
DevConfig->Config.SYNC_DIS4 = 1;
DevConfig->Config.SYNC_DIS6 = 1;
DevConfig->Config.SYNC_DIS8 = 1;
DevConfig->Config.SYNC_DIS10 = 1;
DevConfig->Config.SYNC_DIS12 = 1;
DevConfig->Config.SYNC_DISSYSREF = 1;
DevConfig->Config.CLKin0_TYPE = 0;
DevConfig->Config.CLKin1_TYPE = 0;
DevConfig->Config.CLKin2_TYPE = 0;
DevConfig->Config.CLKin0_EN = 0;
DevConfig->Config.CLKin1_EN = 0;
DevConfig->Config.CLKin2_EN = 0;
DevConfig->Config.CLKin0_OUT_MUX = 3;
// Set CLKin with SPI, release CLKin_SEL0 PIN.
DevConfig->Config.CLKin1_OUT_MUX = 2;
DevConfig->Config.CLKin_SEL_MODE = 1;
// Set CLKin_SEL0 as SPI readback.
DevConfig->Config.CLKin_SEL0_TYPE = 3;
DevConfig->Config.CLKin_SEL0_MUX = 6;
DevConfig->Config.CLKin_SEL1_TYPE = 0;
DevConfig->Config.CLKin_SEL1_MUX = 0;
DevConfig->Config.SDIO_RDBK_TYPE = 0;
DevConfig->Config.RESET_TYPE = 2;
DevConfig->Config.RESET_MUX = 0;
DevConfig->Config.CLKin1_RH = SimpleConfig->Generated.CLKin_R >> 8;
DevConfig->Config.CLKin1_RL = SimpleConfig->Generated.CLKin_R & 0xFF;
DevConfig->Config.PLL1_NH = SimpleConfig->Generated.PLL1_N >> 8;
DevConfig->Config.PLL1_NL = SimpleConfig->Generated.PLL1_N & 0xFF;
DevConfig->Config.PLL1_LD_TYPE = 3;
DevConfig->Config.PLL1_LD_MUX = 1;
DevConfig->Config.PLL2_RH = SimpleConfig->Generated.PLL2_R >> 8;
DevConfig->Config.PLL2_RL = SimpleConfig->Generated.PLL2_R & 0xFF;
DevConfig->Config.PLL2_REF_2X_EN = 0;
DevConfig->Config.PLL2_XTAL_EN = 0;
DevConfig->Config.OSCin_FREQ = 4;
DevConfig->Config.PLL2_P = 2;
DevConfig->Config.PLL2_NH = (SimpleConfig->Generated.PLL2_N >> 16) & 0xFF;
DevConfig->Config.PLL2_FCAL_DIS = 0;
DevConfig->Config.PLL2_NM = (SimpleConfig->Generated.PLL2_N >> 8) & 0xFF;
DevConfig->Config.PLL2_NL = SimpleConfig->Generated.PLL2_N & 0xFF;
DevConfig->Config.PLL2_LD_TYPE = 3;
DevConfig->Config.PLL2_LD_MUX = 2;
for(i = 0; i < 7; i++)
{
if(SimpleConfig->Generated.DCLKout_Div[i] != 0)
{
DevConfig->Config.Clock[i].DCLKout_Div = SimpleConfig->Generated.DCLKout_Div[i];
DevConfig->Config.Clock[i].DCLKout_MUX = 1;
DevConfig->Config.Clock[i].SDCLKout_HS = 1;
DevConfig->Config.Clock[i].SDCLKout_DDLY = 0;
DevConfig->Config.Clock[i].SDCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLKout_PD = 0;
DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0;
DevConfig->Config.Clock[i].CLKout_PD = 0;
DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_HSg_PD = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_FMT = 1;
DevConfig->Config.Clock[i].DCLKout_POL = 0;
DevConfig->Config.Clock[i].SDCLKout_FMT = 1;
DevConfig->Config.Clock[i].SDCLKout_POL = 0;
}
}
return LMK_SUCCESS;
}
int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value)
{
u8 writebuf[3];
writebuf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F);
writebuf[1] = RegisterAddress & 0xFF;
writebuf[2] = Value;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, writebuf, NULL, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
return LMK_SUCCESS;
}
int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value)
{
u8 readbuf[3];
readbuf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F);
readbuf[1] = RegisterAddress & 0xFF;
readbuf[2] = 0;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, readbuf, readbuf, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
*Value = readbuf[2];
return LMK_SUCCESS;
}
#endif //LMK_PRESET_IW_RFSOC_2T2R_EXTERNAL

19
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@ -0,0 +1,19 @@
/*
* LMK_Preset.h
*
* Created on: 2025.01.16
* Author: TiferKing
*/
#ifndef SRC_LMK_PRESET_H_
#define SRC_LMK_PRESET_H_
#include "LMK_ClockTree.h"
#define LMK_PRESET_NONE
//#define LMK_PRESET_IW_RFSOC_2T2R_INTERNAL
//#define LMK_PRESET_IW_RFSOC_2T2R_EXTERNAL
int LMK_ConfigPreset(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
#endif /* SRC_LMK_PRESET_H_ */