Public/LMK04828_Config_Cal
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Add IW-RFSOC-2T2R preset

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This commit is contained in:
Tifer King 2025-01-20 03:19:20 +08:00
parent afa9e1712d
commit ee218d73f6
3 changed files with 42 additions and 204 deletions
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5
LMK_ClockTree.c
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@ -60,6 +60,7 @@ __weak int LMK_CalPLL2CommonRate(LMK_Simple *SimpleConfig)
__weak int LMK_CalRegister(LMK_Simple *SimpleConfig)
{
int i;
LMK_AssertZero(SimpleConfig->SYSREFRate);
LMK_AssertZero(SimpleConfig->Generated.PLL1CommonRate);
LMK_AssertZero(SimpleConfig->Generated.PLL2CommonRate);
@ -69,6 +70,10 @@ __weak int LMK_CalRegister(LMK_Simple *SimpleConfig)
SimpleConfig->Generated.PLL1_N = SimpleConfig->Generated.VCOXClockRate / SimpleConfig->Generated.PLL1CommonRate;
SimpleConfig->Generated.PLL2_R = SimpleConfig->Generated.VCOXClockRate / SimpleConfig->Generated.PLL2CommonRate;
SimpleConfig->Generated.PLL2_N = SimpleConfig->Generated.VCORate / SimpleConfig->Generated.PLL2CommonRate / 2;
for(i = 0; i < 7; i++)
{
SimpleConfig->Generated.DCLKout_Div[i] = SimpleConfig->DClockRate[i] == 0 ? 0 : SimpleConfig->Generated.VCORate / SimpleConfig->DClockRate[i];
}
return LMK_SUCCESS;
}

9
LMK_ClockTree.h
View File

@ -304,16 +304,17 @@ typedef struct LMK_Config_Generated_Type
u16 PLL2_R;
u32 PLL2_N;
u8 VCOSelect;
u8 DCLKout_Div[7];
} LMK_Generated;
typedef struct LMK_Config_Simple_Type
{
void *InterfaceInst;
//Unit Hz;
u64 RefClockRate;
u64 VCOXClockRate;
u64 DClockRate[7];
u64 SYSREFRate;
u64 RefClockRate = 0;
u64 VCOXClockRate = 0;
u64 DClockRate[7] = {0};
u64 SYSREFRate = 0;
//Generated config
LMK_Generated Generated;

232
LMK_Preset.c
View File

@ -14,64 +14,19 @@
#include "xspips.h"
__weak int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig)
{
int i;
// Fixed Register Set
DevConfig->Config.Fixed_0 = 0x7F;
DevConfig->Config.Fixed_1 = 0x01;
DevConfig->Config.Fixed_2 = 0xAA;
DevConfig->Config.Fixed_3 = 0x02;
// Calculate Register Value
DevConfig->Config.OSCout_FMT = 0x00;
DevConfig->Config.OSCout_MUX = 0;
DevConfig->Config.VCO_MUX = VCOSelect;
DevConfig->Config.OSCout_FMT = 0;
DevConfig->Config.OSCout_MUX = 1;
DevConfig->Config.VCO_MUX = SimpleConfig->Generated.VCOSelect;
DevConfig->Config.SYSREF_MUX = 3;
DevConfig->Config.SYSREF_CLKin0_MUX = 0;
DevConfig->Config.SYSREF_DIVH = (VCORate / SimpleConfig->SYSREFRate) >> 8;
DevConfig->Config.SYSREF_DIVL = (VCORate / SimpleConfig->SYSREFRate) & 0xFF;
DevConfig->Config.SYSREF_DDLYH = 0;
DevConfig->Config.SYSREF_DDLYL = 8;
DevConfig->Config.SYSREF_PULSE_CNT = 0x03;
DevConfig->Config.FB_MUX_EN = 0;
DevConfig->Config.FB_MUX = 0;
DevConfig->Config.SYSREF_DIVH = SimpleConfig->Generated.SYSREF_DIV >> 8;
DevConfig->Config.SYSREF_DIVL = SimpleConfig->Generated.SYSREF_DIV & 0xFF;
DevConfig->Config.PLL1_NCLK_MUX = 0;
DevConfig->Config.PLL2_NCLK_MUX = 0;
DevConfig->Config.SYSREF_PLSR_PD = 1;
DevConfig->Config.SYSREF_DDLY_PD = 0;
DevConfig->Config.SYSREF_PD = 1;
DevConfig->Config.SYSREF_GBL_PD = 0;
DevConfig->Config.OSCin_PD = 0;
DevConfig->Config.VCO_PD = 0;
DevConfig->Config.VCO_LDO_PD = 0;
DevConfig->Config.PLL1_PD = 0;
DevConfig->Config.DDLYd0_EN = 0;
DevConfig->Config.DDLYd2_EN = 0;
DevConfig->Config.DDLYd4_EN = 0;
DevConfig->Config.DDLYd6_EN = 0;
DevConfig->Config.DDLYd8_EN = 0;
DevConfig->Config.DDLYd10_EN = 0;
DevConfig->Config.DDLYd12_EN = 0;
DevConfig->Config.DDLYd0_SYSREF_EN = 0;
DevConfig->Config.DDLYd_STEP_CNT = 0;
DevConfig->Config.SYNC_MODE = 1;
DevConfig->Config.SYNC_PLL1_DLD = 0;
DevConfig->Config.SYNC_PLL2_DLD = 0;
DevConfig->Config.SYNC_EN = 1;
DevConfig->Config.SYNC_POL = 0;
DevConfig->Config.SYNC_1SHOT_EN = 0;
DevConfig->Config.SYSREF_CLR = 1;
DevConfig->Config.SYNC_DIS0 = 1;
DevConfig->Config.SYNC_DIS2 = 1;
DevConfig->Config.SYNC_DIS4 = 1;
@ -80,202 +35,79 @@ __weak int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig
DevConfig->Config.SYNC_DIS10 = 1;
DevConfig->Config.SYNC_DIS12 = 1;
DevConfig->Config.SYNC_DISSYSREF = 1;
DevConfig->Config.CLKin0_TYPE = 0;
DevConfig->Config.CLKin1_TYPE = 0;
DevConfig->Config.CLKin2_TYPE = 0;
DevConfig->Config.CLKin0_EN = 0;
DevConfig->Config.CLKin1_EN = 0;
DevConfig->Config.CLKin2_EN = 0;
DevConfig->Config.CLKin0_OUT_MUX = 3;
// Set CLKin with SPI, release CLKin_SEL0 PIN.
DevConfig->Config.CLKin1_OUT_MUX = 3;
DevConfig->Config.CLKin_SEL_MODE = 2;
DevConfig->Config.CLKin_SEL_POL = 0;
// Set CLKin_SEL0 as SPI readback.
DevConfig->Config.CLKin_SEL0_TYPE = 3;
DevConfig->Config.CLKin_SEL0_MUX = 6;
DevConfig->Config.CLKin_SEL1_TYPE = 0;
DevConfig->Config.CLKin_SEL1_MUX = 0;
DevConfig->Config.SDIO_RDBK_TYPE = 0;
DevConfig->Config.RESET_TYPE = 2;
DevConfig->Config.RESET_MUX = 0;
DevConfig->Config.MAN_DACH = 2;
DevConfig->Config.MAN_DAC_EN = 1;
DevConfig->Config.HOLDOVER_FORCE = 0;
DevConfig->Config.TRACK_EN = 1;
DevConfig->Config.LOS_EN = 0;
DevConfig->Config.LOS_TIMEOUT = 0;
DevConfig->Config.MAN_DACL = 0;
DevConfig->Config.DAC_TRIP_LOW = 0;
DevConfig->Config.DAC_TRIP_HIGH = 0;
DevConfig->Config.DAC_CLK_MULT = 0;
DevConfig->Config.DAC_CLK_CNTR = 0x7F;
DevConfig->Config.HOLDOVER_EN = 1;
DevConfig->Config.HOLDOVER_HITLESS_SW = 1;
DevConfig->Config.HOLDOVER_VTUNE_DET = 0;
DevConfig->Config.HOLDOVER_LOS_DET = 0;
DevConfig->Config.HOLDOVER_PLL1_DET = 0;
DevConfig->Config.CLKin_OVERRIDE = 0;
DevConfig->Config.HOLDOVER_DLD_CNTH = 2;
DevConfig->Config.HOLDOVER_DLD_CNTL = 0;
DevConfig->Config.CLKin0_RH = 0;
DevConfig->Config.CLKin0_RL = 120;
DevConfig->Config.CLKin1_RH = 0;
DevConfig->Config.CLKin1_RL = 150;
DevConfig->Config.CLKin2_RH = (SimpleConfig->RefClockRate / PLL1CommonRate) >> 8;
DevConfig->Config.CLKin2_RL = (SimpleConfig->RefClockRate / PLL1CommonRate) & 0xFF;
DevConfig->Config.PLL1_NH = (SimpleConfig->VCOXClockRate / PLL1CommonRate) >> 8;
DevConfig->Config.PLL1_NL = ((SimpleConfig->VCOXClockRate / PLL1CommonRate) & 0xFF);
DevConfig->Config.PLL1_CP_GAIN = 15;
DevConfig->Config.PLL1_CP_POL = 1;
DevConfig->Config.PLL1_CP_TRI = 0;
DevConfig->Config.PLL1_WND_SIZE = 3;
DevConfig->Config.PLL1_DLD_CNTH = 32;
DevConfig->Config.PLL1_DLD_CNTL = 0;
DevConfig->Config.PLL1_N_DLY = 0;
DevConfig->Config.PLL1_R_DLY = 0;
DevConfig->Config.CLKin2_RH = SimpleConfig->Generated.CLKin_R >> 8;
DevConfig->Config.CLKin2_RL = SimpleConfig->Generated.CLKin_R & 0xFF;
DevConfig->Config.PLL1_NH = SimpleConfig->Generated.PLL1_N >> 8;
DevConfig->Config.PLL1_NL = SimpleConfig->Generated.PLL1_N & 0xFF;
DevConfig->Config.PLL1_LD_TYPE = 3;
DevConfig->Config.PLL1_LD_MUX = 1;
DevConfig->Config.PLL2_RH = (SimpleConfig->VCOXClockRate / PLL2CommonRate) >> 8;
DevConfig->Config.PLL2_RL = (SimpleConfig->VCOXClockRate / PLL2CommonRate) & 0xFF;
DevConfig->Config.PLL2_RH = SimpleConfig->Generated.PLL2_R >> 8;
DevConfig->Config.PLL2_RL = SimpleConfig->Generated.PLL2_R & 0xFF;
DevConfig->Config.PLL2_REF_2X_EN = 0;
DevConfig->Config.PLL2_XTAL_EN = 0;
DevConfig->Config.OSCin_FREQ = 4;
DevConfig->Config.PLL2_P = 2;
DevConfig->Config.PLL2_N_CALH = 0;
DevConfig->Config.PLL2_N_CALM = 0;
DevConfig->Config.PLL2_N_CALL = 12;
DevConfig->Config.PLL2_NH = ((VCORate / PLL2CommonRate / 2) >> 16) & 0xFF;
DevConfig->Config.PLL2_NH = (SimpleConfig->Generated.PLL2_N >> 16) & 0xFF;
DevConfig->Config.PLL2_FCAL_DIS = 0;
DevConfig->Config.PLL2_NM = ((VCORate / PLL2CommonRate / 2) >> 8) & 0xFF;
DevConfig->Config.PLL2_NL = (VCORate / PLL2CommonRate / 2) & 0xFF;
DevConfig->Config.PLL2_CP_TRI = 0;
DevConfig->Config.PLL2_CP_POL = 0;
DevConfig->Config.PLL2_CP_GAIN = 3;
DevConfig->Config.PLL2_WND_SIZE = 2;
DevConfig->Config.PLL2_DLD_CNTH = 32;
DevConfig->Config.SYSREF_REQ_EN = 1;
DevConfig->Config.PLL2_DLD_CNTL = 0;
DevConfig->Config.PLL2_LF_R3 = 0;
DevConfig->Config.PLL2_LF_R4 = 0;
DevConfig->Config.PLL2_LF_C3 = 0;
DevConfig->Config.PLL2_LF_C4 = 0;
DevConfig->Config.PLL2_NM = (SimpleConfig->Generated.PLL2_N >> 8) & 0xFF;
DevConfig->Config.PLL2_NL = SimpleConfig->Generated.PLL2_N & 0xFF;
DevConfig->Config.PLL2_LD_TYPE = 3;
DevConfig->Config.PLL2_LD_MUX = 2;
DevConfig->Config.PLL2_PD = 0;
DevConfig->Config.PLL2_PRE_PD = 0;
DevConfig->Config.VCO1_DIV = 0;
for(i = 0; i < 7; i++)
{
if(VCORate / SimpleConfig->DClockRate[i] != 0)
if(SimpleConfig->Generated.DCLKout_Div[i] != 0)
{
DevConfig->Config.Clock[i].DCLKout_Div = VCORate / SimpleConfig->DClockRate[i];
DevConfig->Config.Clock[i].CLKout_IDL = 0;
DevConfig->Config.Clock[i].CLKout_ODL = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 2;
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 2;
DevConfig->Config.Clock[i].DCLKout_Div = SimpleConfig->Generated.DCLKout_Div[i];
DevConfig->Config.Clock[i].DCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_ALDY = 0;
DevConfig->Config.Clock[i].SDCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLKout_HS = 1;
DevConfig->Config.Clock[i].SDCLKout_DDLY = 0;
DevConfig->Config.Clock[i].SDCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLK_ADLY = 0;
DevConfig->Config.Clock[i].SDCLKout_ADLY_EN = 0;
DevConfig->Config.Clock[i].SDCLKout_PD = 0;
DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0;
DevConfig->Config.Clock[i].CLKout_PD = 0;
DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_HSg_PD = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_FMT = 1;
DevConfig->Config.Clock[i].DCLKout_POL = 0;
DevConfig->Config.Clock[i].SDCLKout_FMT = 1;
DevConfig->Config.Clock[i].SDCLKout_POL = 0;
}
else
{
DevConfig->Config.Clock[i].DCLKout_Div = 0;
DevConfig->Config.Clock[i].CLKout_IDL = 0;
DevConfig->Config.Clock[i].CLKout_ODL = 0;
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 5;
DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 5;
DevConfig->Config.Clock[i].DCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_ALDY = 0;
DevConfig->Config.Clock[i].SDCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLKout_DDLY = 0;
DevConfig->Config.Clock[i].SDCLKout_MUX = 1;
DevConfig->Config.Clock[i].DCLKout_HS = 0;
DevConfig->Config.Clock[i].SDCLK_ADLY = 0;
DevConfig->Config.Clock[i].SDCLKout_ADLY_EN = 0;
DevConfig->Config.Clock[i].SDCLKout_PD = 1;
DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0;
DevConfig->Config.Clock[i].CLKout_PD = 1;
DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_HSg_PD = 1;
DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 1;
DevConfig->Config.Clock[i].DCLKout_FMT = 0;
DevConfig->Config.Clock[i].DCLKout_POL = 0;
DevConfig->Config.Clock[i].SDCLKout_FMT = 0;
DevConfig->Config.Clock[i].SDCLKout_POL = 0;
}
}
return LMK_SUCCESS;
}
int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value)
{
u8 buf[3];
u8 writebuf[3];
buf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F);
buf[1] = RegisterAddress & 0xFF;
buf[2] = Value;
writebuf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F);
writebuf[1] = RegisterAddress & 0xFF;
writebuf[2] = Value;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, NULL, 3);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, writebuf, NULL, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
return LMK_SUCCESS;
@ -283,17 +115,17 @@ int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value)
int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value)
{
u8 buf[3];
u8 readbuf[3];
buf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F);
buf[1] = RegisterAddress & 0xFF;
buf[2] = 0;
readbuf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F);
readbuf[1] = RegisterAddress & 0xFF;
readbuf[2] = 0;
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, buf, 3);
XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, readbuf, readbuf, 3);
XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F);
*Value = buf[2];
*Value = readbuf[2];
return LMK_SUCCESS;
}