340 lines
7.1 KiB
C
340 lines
7.1 KiB
C
/*
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* LMK_ClockTree.h
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*
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* Created on: 2019年3月5日
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* Author: TiferKing
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*/
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#ifndef SRC_LMK_CLOCKTREE_H_
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#define SRC_LMK_CLOCKTREE_H_
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#include "xstatus.h"
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#include "ConfigCalculate.h"
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#define __weak __attribute__((weak))
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#define UNUSED(x) (void)x
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#define LMK_SUCCESS 0
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#define LMK_FAILURE 1
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#define LMK_AssertInValid(Expression) \
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{ \
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if ((Expression) < 1000) { \
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return LMK_FAILURE; \
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} \
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}
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#define LMK_AssertZero(Expression) \
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{ \
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if ((Expression) == 0) { \
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return LMK_FAILURE; \
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} \
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}
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#define LMK_AssertFailure(Expression) \
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{ \
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if ((Expression) != LMK_SUCCESS) { \
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return LMK_FAILURE; \
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} \
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}
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#define LMK_VCO0_RATE_L 2370000000
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#define LMK_VCO0_RATE_H 2630000000
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#define LMK_VCO1_RATE_L 2920000000
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#define LMK_VCO1_RATE_H 3080000000
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#define LMK_VCOX_RATE_L 122867712
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#define LMK_VCOX_RATE_H 122892288
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#define LMK_PLL1_LFBAND 80000
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#define LMK_PLL2_LFBAND 160000
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// LMK Clock Channel Register Map
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typedef struct LMK_ClockPair_Type
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{
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u8 DCLKout_Div :4,
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CLKout_IDL :1,
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CLKout_ODL :1,
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:1;
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u8 DCLKout_DDLY_CNTL :4,
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DCLKout_DDLY_CNTH :4;
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u8 :8;
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u8 DCLKout_MUX :2,
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DCLKout_ADLY_MUX :1,
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DCLKout_ALDY :5;
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u8 SDCLKout_HS :1,
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SDCLKout_DDLY :4,
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SDCLKout_MUX :1,
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DCLKout_HS :1,
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:1;
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u8 SDCLK_ADLY :4,
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SDCLKout_ADLY_EN :1,
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:3;
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u8 SDCLKout_PD :1,
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SDCLKout_DIS_MODE :2,
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CLKout_PD :1,
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DCLKout_ADLY_PD :1,
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DCLKout_ADLYg_PD :1,
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DCLKout_HSg_PD :1,
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DCLKout_DDLY_PD :1;
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u8 DCLKout_FMT :3,
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DCLKout_POL :1,
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SDCLKout_FMT :3,
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SDCLKout_POL :1;
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} LMK_ClockPair;
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// LMK Register Map
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typedef struct LMK_RegMap_Type
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{
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/******************************///Addr : 0x100
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LMK_ClockPair Clock[7];
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/******************************///Addr : 0x138
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u8 OSCout_FMT :4,
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OSCout_MUX :1,
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VCO_MUX :2,
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:1;
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u8 SYSREF_MUX :2,
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SYSREF_CLKin0_MUX :1,
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:5;
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u8 SYSREF_DIVH :5,
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:3;
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u8 SYSREF_DIVL :8;
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u8 SYSREF_DDLYH :5,
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:3;
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u8 SYSREF_DDLYL :8;
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u8 SYSREF_PULSE_CNT :2,
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:6;
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u8 FB_MUX_EN :1,
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FB_MUX :2,
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PLL1_NCLK_MUX :1,
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PLL2_NCLK_MUX :1,
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:3;
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/******************************///Addr : 0x140
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u8 SYSREF_PLSR_PD :1,
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SYSREF_DDLY_PD :1,
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SYSREF_PD :1,
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SYSREF_GBL_PD :1,
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OSCin_PD :1,
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VCO_PD :1,
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VCO_LDO_PD :1,
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PLL1_PD :1;
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u8 DDLYd0_EN :1,
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DDLYd2_EN :1,
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DDLYd4_EN :1,
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DDLYd6_EN :1,
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DDLYd8_EN :1,
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DDLYd10_EN :1,
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DDLYd12_EN :1,
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DDLYd0_SYSREF_EN :1;
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u8 DDLYd_STEP_CNT :4,
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:4;
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u8 SYNC_MODE :2,
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SYNC_PLL1_DLD :1,
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SYNC_PLL2_DLD :1,
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SYNC_EN :1,
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SYNC_POL :1,
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SYNC_1SHOT_EN :1,
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SYSREF_CLR :1;
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u8 SYNC_DIS0 :1,
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SYNC_DIS2 :1,
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SYNC_DIS4 :1,
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SYNC_DIS6 :1,
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SYNC_DIS8 :1,
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SYNC_DIS10 :1,
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SYNC_DIS12 :1,
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SYNC_DISSYSREF :1;
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u8 Fixed_0 :8; //Fixed 0x7F
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u8 CLKin0_TYPE :1,
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CLKin1_TYPE :1,
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CLKin2_TYPE :1,
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CLKin0_EN :1,
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CLKin1_EN :1,
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CLKin2_EN :1,
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:2;
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u8 CLKin0_OUT_MUX :2,
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CLKin1_OUT_MUX :2,
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CLKin_SEL_MODE :3,
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CLKin_SEL_POL :1;
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u8 CLKin_SEL0_TYPE :3,
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CLKin_SEL0_MUX :3,
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:2;
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u8 CLKin_SEL1_TYPE :3,
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CLKin_SEL1_MUX :3,
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SDIO_RDBK_TYPE :1,
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:1;
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u8 RESET_TYPE :3,
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RESET_MUX :3,
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:2;
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u8 MAN_DACH :2,
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MAN_DAC_EN :1,
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HOLDOVER_FORCE :1,
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TRACK_EN :1,
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LOS_EN :1,
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LOS_TIMEOUT :2;
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u8 MAN_DACL :8;
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u8 DAC_TRIP_LOW :6,
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:2;
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u8 DAC_TRIP_HIGH :6,
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DAC_CLK_MULT :2;
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u8 DAC_CLK_CNTR :8;
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/******************************///Addr : 0x150
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u8 HOLDOVER_EN :1,
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HOLDOVER_HITLESS_SW :1,
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HOLDOVER_VTUNE_DET :1,
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HOLDOVER_LOS_DET :1,
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HOLDOVER_PLL1_DET :1,
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:1,
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CLKin_OVERRIDE :1,
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:1;
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u8 HOLDOVER_DLD_CNTH :6,
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:2;
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u8 HOLDOVER_DLD_CNTL :8;
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u8 CLKin0_RH :6,
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:2;
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u8 CLKin0_RL :8;
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u8 CLKin1_RH :6,
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:2;
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u8 CLKin1_RL :8;
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u8 CLKin2_RH :6,
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:2;
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u8 CLKin2_RL :8;
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u8 PLL1_NH :6,
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:2;
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u8 PLL1_NL :8;
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u8 PLL1_CP_GAIN :4,
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PLL1_CP_POL :1,
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PLL1_CP_TRI :1,
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PLL1_WND_SIZE :2;
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u8 PLL1_DLD_CNTH :6,
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:2;
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u8 PLL1_DLD_CNTL :8;
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u8 PLL1_N_DLY :3,
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PLL1_R_DLY :3,
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:2;
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u8 PLL1_LD_TYPE :3,
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PLL1_LD_MUX :5;
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/******************************///Addr : 0x160
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u8 PLL2_RH :4,
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:4;
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u8 PLL2_RL :8;
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u8 PLL2_REF_2X_EN :1,
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PLL2_XTAL_EN :1,
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OSCin_FREQ :3,
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PLL2_P :3;
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u8 PLL2_N_CALH :2,
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:6;
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u8 PLL2_N_CALM :8;
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u8 PLL2_N_CALL :8;
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u8 PLL2_NH :2,
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PLL2_FCAL_DIS :1,
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:5;
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u8 PLL2_NM :8;
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u8 PLL2_NL :8;
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u8 Fixed_1 :1, //Fixed 0x01
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PLL2_CP_TRI :1,
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PLL2_CP_POL :1,
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PLL2_CP_GAIN :2,
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PLL2_WND_SIZE :2,
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:1;
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u8 PLL2_DLD_CNTH :6,
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SYSREF_REQ_EN :1,
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:1;
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u8 PLL2_DLD_CNTL :8;
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u8 PLL2_LF_R3 :3,
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PLL2_LF_R4 :3,
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:2;
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u8 PLL2_LF_C3 :4,
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PLL2_LF_C4 :4;
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u8 PLL2_LD_TYPE :3,
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PLL2_LD_MUX :5;
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u8 :8;
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/******************************///Addr : 0x170
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u8 :8;
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u8 Fixed_2 :8; //Fixed 0xAA
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u8 Fixed_3 :8; //Fixed 0x02
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u8 :5,
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PLL2_PD :1,
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PLL2_PRE_PD :1,
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:1;
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u8 VCO1_DIV :5,
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:3;
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} LMK_RegMap;
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// LMK Reg Read Back Map
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typedef struct LMK_ReadBack_Type
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{
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//Addr : 0x182
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u8 CLR_PLL1_LD_LOST :1,
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RB_PLL1_LD :1,
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RB_PLL1_LD_LOST :1,
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:5;
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u8 CLR_PLL2_LD_LOST :1,
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RB_PLL2_LD :1,
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RB_PLL2_LD_LOST :1,
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:5;
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u8 RB_CLKin0_LOS :1,
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RB_CLKin1_LOS :1,
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:1,
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RB_CLKin0_SEL :1,
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RB_CLKin1_SEL :1,
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RB_CLKin2_SEL :1,
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RB_DAC_VALUEH :2;
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u8 RB_DAC_VALUEL :8;
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u8 :8;
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u8 :8;
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u8 :4,
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RB_HOLDOVER :1,
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:3;
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} LMK_ReadBack;
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typedef struct LMK_Config_Type
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{
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void *InterfaceInst;
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LMK_RegMap Config;
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LMK_ReadBack Status;
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} LMK_Config;
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typedef struct LMK_Config_Generated_Type
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{
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u64 PLL1CommonRate;
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u64 PLL2CommonRate;
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u64 VCORate;
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u16 SYSREF_DIV;
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u16 CLKin_R;
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u16 PLL1_N;
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u16 PLL2_R;
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u32 PLL2_N;
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u8 VCOSelect;
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u8 DCLKout_Div[7];
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} LMK_Generated;
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typedef struct LMK_Config_Simple_Type
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{
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void *InterfaceInst;
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//Unit Hz;
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u64 RefClockRate;
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u64 VCOXClockRate;
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u64 DClockRate[7];
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u64 SYSREFRate;
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//Generated config
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LMK_Generated Generated;
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} LMK_Simple;
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int LMK_CalPLL1CommonRate(LMK_Simple *SimpleConfig);
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int LMK_CalPLL2CommonRate(LMK_Simple *SimpleConfig);
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int LMK_CalRegister(LMK_Simple *SimpleConfig);
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int LMK_ConfigInitRegister(LMK_Config *DevConfig);
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int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
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int LMK_ConfigPreset(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
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int LMK_ConfigCustomize(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
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int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig);
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int LMK_Init(LMK_Config *DevConfig);
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int LMK_StatusRead(LMK_Config *DevConfig);
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int LMK_RegLock(LMK_Config *DevConfig);
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int LMK_RegUnlock(LMK_Config *DevConfig);
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int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value);
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int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value);
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#endif /* SRC_LMK_CLOCKTREE_H_ */
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