/* * LMK_ClockTree.h * * Created on: 2019年3月5日 * Author: TiferKing */ #ifndef SRC_LMK_CLOCKTREE_H_ #define SRC_LMK_CLOCKTREE_H_ #include "xstatus.h" #include "ConfigCalculate.h" #define __weak __attribute__((weak)) #define UNUSED(x) (void)x #define LMK_SUCCESS 0 #define LMK_FAILURE 1 #define LMK_AssertInValid(Expression) \ { \ if ((Expression) < 1000) { \ return LMK_FAILURE; \ } \ } #define LMK_AssertZero(Expression) \ { \ if ((Expression) == 0) { \ return LMK_FAILURE; \ } \ } #define LMK_AssertFailure(Expression) \ { \ if ((Expression) != LMK_SUCCESS) { \ return LMK_FAILURE; \ } \ } #define LMK_VCO0_RATE_L 2370000000 #define LMK_VCO0_RATE_H 2630000000 #define LMK_VCO1_RATE_L 2920000000 #define LMK_VCO1_RATE_H 3080000000 #define LMK_VCOX_RATE_L 122867712 #define LMK_VCOX_RATE_H 122892288 #define LMK_PLL1_LFBAND 80000 #define LMK_PLL2_LFBAND 160000 // LMK Clock Channel Register Map typedef struct LMK_ClockPair_Type { u8 DCLKout_Div :4, CLKout_IDL :1, CLKout_ODL :1, :1; u8 DCLKout_DDLY_CNTL :4, DCLKout_DDLY_CNTH :4; u8 :8; u8 DCLKout_MUX :2, DCLKout_ADLY_MUX :1, DCLKout_ALDY :5; u8 SDCLKout_HS :1, SDCLKout_DDLY :4, SDCLKout_MUX :1, DCLKout_HS :1, :1; u8 SDCLK_ADLY :4, SDCLKout_ADLY_EN :1, :3; u8 SDCLKout_PD :1, SDCLKout_DIS_MODE :2, CLKout_PD :1, DCLKout_ADLY_PD :1, DCLKout_ADLYg_PD :1, DCLKout_HSg_PD :1, DCLKout_DDLY_PD :1; u8 DCLKout_FMT :3, DCLKout_POL :1, SDCLKout_FMT :3, SDCLKout_POL :1; } LMK_ClockPair; // LMK Register Map typedef struct LMK_RegMap_Type { /******************************///Addr : 0x100 LMK_ClockPair Clock[7]; /******************************///Addr : 0x138 u8 OSCout_FMT :4, OSCout_MUX :1, VCO_MUX :2, :1; u8 SYSREF_MUX :2, SYSREF_CLKin0_MUX :1, :5; u8 SYSREF_DIVH :5, :3; u8 SYSREF_DIVL :8; u8 SYSREF_DDLYH :5, :3; u8 SYSREF_DDLYL :8; u8 SYSREF_PULSE_CNT :2, :6; u8 FB_MUX_EN :1, FB_MUX :2, PLL1_NCLK_MUX :1, PLL2_NCLK_MUX :1, :3; /******************************///Addr : 0x140 u8 SYSREF_PLSR_PD :1, SYSREF_DDLY_PD :1, SYSREF_PD :1, SYSREF_GBL_PD :1, OSCin_PD :1, VCO_PD :1, VCO_LDO_PD :1, PLL1_PD :1; u8 DDLYd0_EN :1, DDLYd2_EN :1, DDLYd4_EN :1, DDLYd6_EN :1, DDLYd8_EN :1, DDLYd10_EN :1, DDLYd12_EN :1, DDLYd0_SYSREF_EN :1; u8 DDLYd_STEP_CNT :4, :4; u8 SYNC_MODE :2, SYNC_PLL1_DLD :1, SYNC_PLL2_DLD :1, SYNC_EN :1, SYNC_POL :1, SYNC_1SHOT_EN :1, SYSREF_CLR :1; u8 SYNC_DIS0 :1, SYNC_DIS2 :1, SYNC_DIS4 :1, SYNC_DIS6 :1, SYNC_DIS8 :1, SYNC_DIS10 :1, SYNC_DIS12 :1, SYNC_DISSYSREF :1; u8 Fixed_0 :8; //Fixed 0x7F u8 CLKin0_TYPE :1, CLKin1_TYPE :1, CLKin2_TYPE :1, CLKin0_EN :1, CLKin1_EN :1, CLKin2_EN :1, :2; u8 CLKin0_OUT_MUX :2, CLKin1_OUT_MUX :2, CLKin_SEL_MODE :3, CLKin_SEL_POL :1; u8 CLKin_SEL0_TYPE :3, CLKin_SEL0_MUX :3, :2; u8 CLKin_SEL1_TYPE :3, CLKin_SEL1_MUX :3, SDIO_RDBK_TYPE :1, :1; u8 RESET_TYPE :3, RESET_MUX :3, :2; u8 MAN_DACH :2, MAN_DAC_EN :1, HOLDOVER_FORCE :1, TRACK_EN :1, LOS_EN :1, LOS_TIMEOUT :2; u8 MAN_DACL :8; u8 DAC_TRIP_LOW :6, :2; u8 DAC_TRIP_HIGH :6, DAC_CLK_MULT :2; u8 DAC_CLK_CNTR :8; /******************************///Addr : 0x150 u8 HOLDOVER_EN :1, HOLDOVER_HITLESS_SW :1, HOLDOVER_VTUNE_DET :1, HOLDOVER_LOS_DET :1, HOLDOVER_PLL1_DET :1, :1, CLKin_OVERRIDE :1, :1; u8 HOLDOVER_DLD_CNTH :6, :2; u8 HOLDOVER_DLD_CNTL :8; u8 CLKin0_RH :6, :2; u8 CLKin0_RL :8; u8 CLKin1_RH :6, :2; u8 CLKin1_RL :8; u8 CLKin2_RH :6, :2; u8 CLKin2_RL :8; u8 PLL1_NH :6, :2; u8 PLL1_NL :8; u8 PLL1_CP_GAIN :4, PLL1_CP_POL :1, PLL1_CP_TRI :1, PLL1_WND_SIZE :2; u8 PLL1_DLD_CNTH :6, :2; u8 PLL1_DLD_CNTL :8; u8 PLL1_N_DLY :3, PLL1_R_DLY :3, :2; u8 PLL1_LD_TYPE :3, PLL1_LD_MUX :5; /******************************///Addr : 0x160 u8 PLL2_RH :4, :4; u8 PLL2_RL :8; u8 PLL2_REF_2X_EN :1, PLL2_XTAL_EN :1, OSCin_FREQ :3, PLL2_P :3; u8 PLL2_N_CALH :2, :6; u8 PLL2_N_CALM :8; u8 PLL2_N_CALL :8; u8 PLL2_NH :2, PLL2_FCAL_DIS :1, :5; u8 PLL2_NM :8; u8 PLL2_NL :8; u8 Fixed_1 :1, //Fixed 0x01 PLL2_CP_TRI :1, PLL2_CP_POL :1, PLL2_CP_GAIN :2, PLL2_WND_SIZE :2, :1; u8 PLL2_DLD_CNTH :6, SYSREF_REQ_EN :1, :1; u8 PLL2_DLD_CNTL :8; u8 PLL2_LF_R3 :3, PLL2_LF_R4 :3, :2; u8 PLL2_LF_C3 :4, PLL2_LF_C4 :4; u8 PLL2_LD_TYPE :3, PLL2_LD_MUX :5; u8 :8; /******************************///Addr : 0x170 u8 :8; u8 Fixed_2 :8; //Fixed 0xAA u8 Fixed_3 :8; //Fixed 0x02 u8 :5, PLL2_PD :1, PLL2_PRE_PD :1, :1; u8 VCO1_DIV :5, :3; } LMK_RegMap; // LMK Reg Read Back Map typedef struct LMK_ReadBack_Type { //Addr : 0x182 u8 CLR_PLL1_LD_LOST :1, RB_PLL1_LD :1, RB_PLL1_LD_LOST :1, :5; u8 CLR_PLL2_LD_LOST :1, RB_PLL2_LD :1, RB_PLL2_LD_LOST :1, :5; u8 RB_CLKin0_LOS :1, RB_CLKin1_LOS :1, :1, RB_CLKin0_SEL :1, RB_CLKin1_SEL :1, RB_CLKin2_SEL :1, RB_DAC_VALUEH :2; u8 RB_DAC_VALUEL :8; u8 :8; u8 :8; u8 :4, RB_HOLDOVER :1, :3; } LMK_ReadBack; typedef struct LMK_Config_Type { void *InterfaceInst; LMK_RegMap Config; LMK_ReadBack Status; } LMK_Config; typedef struct LMK_Config_Generated_Type { u64 PLL1CommonRate; u64 PLL2CommonRate; u64 VCORate; u16 SYSREF_DIV; u16 CLKin_R; u16 PLL1_N; u16 PLL2_R; u32 PLL2_N; u8 VCOSelect; u8 DCLKout_Div[7]; } LMK_Generated; typedef struct LMK_Config_Simple_Type { void *InterfaceInst; //Unit Hz; u64 RefClockRate; u64 VCOXClockRate; u64 DClockRate[7]; u64 SYSREFRate; //Generated config LMK_Generated Generated; } LMK_Simple; int LMK_CalPLL1CommonRate(LMK_Simple *SimpleConfig); int LMK_CalPLL2CommonRate(LMK_Simple *SimpleConfig); int LMK_CalRegister(LMK_Simple *SimpleConfig); int LMK_ConfigInitRegister(LMK_Config *DevConfig); int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig); int LMK_ConfigPreset(LMK_Config *DevConfig, LMK_Simple *SimpleConfig); int LMK_ConfigCustomize(LMK_Config *DevConfig, LMK_Simple *SimpleConfig); int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig); int LMK_Init(LMK_Config *DevConfig); int LMK_StatusRead(LMK_Config *DevConfig); int LMK_RegLock(LMK_Config *DevConfig); int LMK_RegUnlock(LMK_Config *DevConfig); int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value); int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value); #endif /* SRC_LMK_CLOCKTREE_H_ */