diff --git a/ConfigCalculate.c b/ConfigCalculate.c new file mode 100644 index 0000000..30a89e6 --- /dev/null +++ b/ConfigCalculate.c @@ -0,0 +1,27 @@ +/* + * ConfigCalculate.c + * + * Created on: 2019Äê3ÔÂ15ÈÕ + * Author: TiferKing + */ + +#include "ConfigCalculate.h" + +__weak u64 GreatestCommonDivisor(u64 a, u64 b) +{ + u64 c; + while(b != 0) + { + c = a % b; + a = b; + b = c; + } + return a; +} + +__weak u64 LeastCommonMultiple(u64 a, u64 b) +{ + u64 c; + c = GreatestCommonDivisor(a,b); + return a / c * b; +} diff --git a/ConfigCalculate.h b/ConfigCalculate.h new file mode 100644 index 0000000..c7f068f --- /dev/null +++ b/ConfigCalculate.h @@ -0,0 +1,19 @@ +/* + * ConfigCalculate.h + * + * Created on: 2019��3��15�� + * Author: TiferKing + */ + +#ifndef SRC_CONFIGCALCULATE_H_ +#define SRC_CONFIGCALCULATE_H_ + +#include "xil_types.h" + +#define __weak __attribute__((weak)) +#define UNUSED(x) (void)x + +u64 LeastCommonMultiple(u64 a, u64 b); +u64 GreatestCommonDivisor(u64 a, u64 b); + +#endif /* SRC_CONFIGCALCULATE_H_ */ diff --git a/LMK_ClockTree.c b/LMK_ClockTree.c new file mode 100644 index 0000000..a804931 --- /dev/null +++ b/LMK_ClockTree.c @@ -0,0 +1,455 @@ +/* + * LMK_ClockTree.c + * + * Created on: 2019��3��5�� + * Author: TiferKing + */ + +#include "LMK_ClockTree.h" + +__weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) +{ + int i; + u64 ChMaxRate; + u64 VCORate; + u64 PLL1CommonRate; + u64 PLL2CommonRate; + u64 RootDiv; + //u64 PLLDiv; + u8 VCOSelect; + + DevConfig->InterfaceInst = SimpleConfig->InterfaceInst; + + + PLL1CommonRate = GreatestCommonDivisor(SimpleConfig->RefClockRate, SimpleConfig->VCOXClockRate); + /*if(PLL1CommonRate > LMK_PLL1_LFBAND) + { + PLLDiv = PLL1CommonRate / LMK_PLL1_LFBAND; + PLL1CommonRate /= PLLDiv + 1; + }*/ + if(PLL1CommonRate < 1000) + { + return XST_FAILURE; + } + + ChMaxRate = 0; + for(i = 0; i < 7; i++) + { + if(SimpleConfig->DClockRate[i] != 0) + { + if(ChMaxRate != 0) + { + ChMaxRate = LeastCommonMultiple(ChMaxRate, SimpleConfig->DClockRate[i]); + } + else + { + ChMaxRate = SimpleConfig->DClockRate[i]; + } + } + } + + if(ChMaxRate == 0) + { + return XST_FAILURE; + } + + if((LMK_VCO0_RATE_L / ChMaxRate) < (LMK_VCO0_RATE_H / ChMaxRate)) + { + RootDiv = (LMK_VCO0_RATE_L / ChMaxRate) + 1; + VCORate = RootDiv * ChMaxRate; + VCOSelect = 0; + } + else if((LMK_VCO1_RATE_L / ChMaxRate) < (LMK_VCO1_RATE_H / ChMaxRate)) + { + RootDiv = (LMK_VCO1_RATE_L / ChMaxRate) + 1; + VCORate = RootDiv * ChMaxRate; + VCOSelect = 1; + } + else + { + return XST_FAILURE; + } + + PLL2CommonRate = GreatestCommonDivisor(VCORate, SimpleConfig->VCOXClockRate * 2) / 2; + /*if(PLL2CommonRate > LMK_PLL2_LFBAND) + { + PLLDiv = PLL2CommonRate / LMK_PLL2_LFBAND; + PLL2CommonRate /= PLLDiv + 1; + }*/ + if(PLL2CommonRate < 1000) + { + return XST_FAILURE; + } + + + // Fixed Register Set + DevConfig->Config.Fixed_0 = 0x7F; + DevConfig->Config.Fixed_1 = 0x01; + DevConfig->Config.Fixed_2 = 0xAA; + DevConfig->Config.Fixed_3 = 0x02; + + // Calculate Register Value + DevConfig->Config.OSCout_FMT = 0x00; + DevConfig->Config.OSCout_MUX = 0; + DevConfig->Config.VCO_MUX = VCOSelect; + + DevConfig->Config.SYSREF_MUX = 3; + DevConfig->Config.SYSREF_CLKin0_MUX = 0; + + DevConfig->Config.SYSREF_DIVH = (VCORate / SimpleConfig->SYSREFRate) >> 8; + DevConfig->Config.SYSREF_DIVL = (VCORate / SimpleConfig->SYSREFRate) & 0xFF; + + DevConfig->Config.SYSREF_DDLYH = 0; + DevConfig->Config.SYSREF_DDLYL = 8; + + DevConfig->Config.SYSREF_PULSE_CNT = 0x03; + + DevConfig->Config.FB_MUX_EN = 0; + DevConfig->Config.FB_MUX = 0; + DevConfig->Config.PLL1_NCLK_MUX = 0; + DevConfig->Config.PLL2_NCLK_MUX = 0; + + DevConfig->Config.SYSREF_PLSR_PD = 1; + DevConfig->Config.SYSREF_DDLY_PD = 0; + DevConfig->Config.SYSREF_PD = 1; + DevConfig->Config.SYSREF_GBL_PD = 0; + DevConfig->Config.OSCin_PD = 0; + DevConfig->Config.VCO_PD = 0; + DevConfig->Config.VCO_LDO_PD = 0; + DevConfig->Config.PLL1_PD = 0; + + DevConfig->Config.DDLYd0_EN = 0; + DevConfig->Config.DDLYd2_EN = 0; + DevConfig->Config.DDLYd4_EN = 0; + DevConfig->Config.DDLYd6_EN = 0; + DevConfig->Config.DDLYd8_EN = 0; + DevConfig->Config.DDLYd10_EN = 0; + DevConfig->Config.DDLYd12_EN = 0; + DevConfig->Config.DDLYd0_SYSREF_EN = 0; + + DevConfig->Config.DDLYd_STEP_CNT = 0; + + DevConfig->Config.SYNC_MODE = 1; + DevConfig->Config.SYNC_PLL1_DLD = 0; + DevConfig->Config.SYNC_PLL2_DLD = 0; + DevConfig->Config.SYNC_EN = 1; + DevConfig->Config.SYNC_POL = 0; + DevConfig->Config.SYNC_1SHOT_EN = 0; + DevConfig->Config.SYSREF_CLR = 1; + + DevConfig->Config.SYNC_DIS0 = 1; + DevConfig->Config.SYNC_DIS2 = 1; + DevConfig->Config.SYNC_DIS4 = 1; + DevConfig->Config.SYNC_DIS6 = 1; + DevConfig->Config.SYNC_DIS8 = 1; + DevConfig->Config.SYNC_DIS10 = 1; + DevConfig->Config.SYNC_DIS12 = 1; + DevConfig->Config.SYNC_DISSYSREF = 1; + + DevConfig->Config.CLKin0_TYPE = 0; + DevConfig->Config.CLKin1_TYPE = 0; + DevConfig->Config.CLKin2_TYPE = 0; + DevConfig->Config.CLKin0_EN = 0; + DevConfig->Config.CLKin1_EN = 0; + DevConfig->Config.CLKin2_EN = 0; + + DevConfig->Config.CLKin0_OUT_MUX = 3; + DevConfig->Config.CLKin1_OUT_MUX = 3; + DevConfig->Config.CLKin_SEL_MODE = 2; + DevConfig->Config.CLKin_SEL_POL = 0; + + DevConfig->Config.CLKin_SEL0_TYPE = 3; + DevConfig->Config.CLKin_SEL0_MUX = 6; + + DevConfig->Config.CLKin_SEL1_TYPE = 0; + DevConfig->Config.CLKin_SEL1_MUX = 0; + DevConfig->Config.SDIO_RDBK_TYPE = 0; + + DevConfig->Config.RESET_TYPE = 2; + DevConfig->Config.RESET_MUX = 0; + + DevConfig->Config.MAN_DACH = 2; + DevConfig->Config.MAN_DAC_EN = 1; + DevConfig->Config.HOLDOVER_FORCE = 0; + DevConfig->Config.TRACK_EN = 1; + DevConfig->Config.LOS_EN = 0; + DevConfig->Config.LOS_TIMEOUT = 0; + + DevConfig->Config.MAN_DACL = 0; + + DevConfig->Config.DAC_TRIP_LOW = 0; + + DevConfig->Config.DAC_TRIP_HIGH = 0; + DevConfig->Config.DAC_CLK_MULT = 0; + + DevConfig->Config.DAC_CLK_CNTR = 0x7F; + + DevConfig->Config.HOLDOVER_EN = 1; + DevConfig->Config.HOLDOVER_HITLESS_SW = 1; + DevConfig->Config.HOLDOVER_VTUNE_DET = 0; + DevConfig->Config.HOLDOVER_LOS_DET = 0; + DevConfig->Config.HOLDOVER_PLL1_DET = 0; + DevConfig->Config.CLKin_OVERRIDE = 0; + + DevConfig->Config.HOLDOVER_DLD_CNTH = 2; + + DevConfig->Config.HOLDOVER_DLD_CNTL = 0; + DevConfig->Config.CLKin0_RH = 0; + DevConfig->Config.CLKin0_RL = 120; + DevConfig->Config.CLKin1_RH = 0; + DevConfig->Config.CLKin1_RL = 150; + DevConfig->Config.CLKin2_RH = (SimpleConfig->RefClockRate / PLL1CommonRate) >> 8; + DevConfig->Config.CLKin2_RL = (SimpleConfig->RefClockRate / PLL1CommonRate) & 0xFF; + + DevConfig->Config.PLL1_NH = (SimpleConfig->VCOXClockRate / PLL1CommonRate) >> 8; + DevConfig->Config.PLL1_NL = ((SimpleConfig->VCOXClockRate / PLL1CommonRate) & 0xFF); + + DevConfig->Config.PLL1_CP_GAIN = 15; + DevConfig->Config.PLL1_CP_POL = 1; + DevConfig->Config.PLL1_CP_TRI = 0; + DevConfig->Config.PLL1_WND_SIZE = 3; + + DevConfig->Config.PLL1_DLD_CNTH = 32; + DevConfig->Config.PLL1_DLD_CNTL = 0; + + DevConfig->Config.PLL1_N_DLY = 0; + DevConfig->Config.PLL1_R_DLY = 0; + + DevConfig->Config.PLL1_LD_TYPE = 3; + DevConfig->Config.PLL1_LD_MUX = 1; + + DevConfig->Config.PLL2_RH = (SimpleConfig->VCOXClockRate / PLL2CommonRate) >> 8; + DevConfig->Config.PLL2_RL = (SimpleConfig->VCOXClockRate / PLL2CommonRate) & 0xFF; + + DevConfig->Config.PLL2_REF_2X_EN = 0; + DevConfig->Config.PLL2_XTAL_EN = 0; + DevConfig->Config.OSCin_FREQ = 4; + DevConfig->Config.PLL2_P = 2; + + DevConfig->Config.PLL2_N_CALH = 0; + DevConfig->Config.PLL2_N_CALM = 0; + DevConfig->Config.PLL2_N_CALL = 12; + + DevConfig->Config.PLL2_NH = ((VCORate / PLL2CommonRate / 2) >> 16) & 0xFF; + DevConfig->Config.PLL2_FCAL_DIS = 0; + DevConfig->Config.PLL2_NM = ((VCORate / PLL2CommonRate / 2) >> 8) & 0xFF; + DevConfig->Config.PLL2_NL = (VCORate / PLL2CommonRate / 2) & 0xFF; + + DevConfig->Config.PLL2_CP_TRI = 0; + DevConfig->Config.PLL2_CP_POL = 0; + DevConfig->Config.PLL2_CP_GAIN = 3; + DevConfig->Config.PLL2_WND_SIZE = 2; + + DevConfig->Config.PLL2_DLD_CNTH = 32; + DevConfig->Config.SYSREF_REQ_EN = 1; + DevConfig->Config.PLL2_DLD_CNTL = 0; + + DevConfig->Config.PLL2_LF_R3 = 0; + DevConfig->Config.PLL2_LF_R4 = 0; + + DevConfig->Config.PLL2_LF_C3 = 0; + DevConfig->Config.PLL2_LF_C4 = 0; + DevConfig->Config.PLL2_LD_TYPE = 3; + DevConfig->Config.PLL2_LD_MUX = 2; + + DevConfig->Config.PLL2_PD = 0; + DevConfig->Config.PLL2_PRE_PD = 0; + + DevConfig->Config.VCO1_DIV = 0; + + for(i = 0; i < 7; i++) + { + if(VCORate / SimpleConfig->DClockRate[i] != 0) + { + DevConfig->Config.Clock[i].DCLKout_Div = VCORate / SimpleConfig->DClockRate[i]; + DevConfig->Config.Clock[i].CLKout_IDL = 0; + DevConfig->Config.Clock[i].CLKout_ODL = 0; + + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 2; + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 2; + + DevConfig->Config.Clock[i].DCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ALDY = 0; + + DevConfig->Config.Clock[i].SDCLKout_HS = 0; + DevConfig->Config.Clock[i].SDCLKout_DDLY = 0; + DevConfig->Config.Clock[i].SDCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_HS = 0; + + DevConfig->Config.Clock[i].SDCLK_ADLY = 0; + DevConfig->Config.Clock[i].SDCLKout_ADLY_EN = 0; + + DevConfig->Config.Clock[i].SDCLKout_PD = 0; + DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0; + DevConfig->Config.Clock[i].CLKout_PD = 0; + DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1; + DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1; + DevConfig->Config.Clock[i].DCLKout_HSg_PD = 0; + DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 0; + + DevConfig->Config.Clock[i].DCLKout_FMT = 1; + DevConfig->Config.Clock[i].DCLKout_POL = 0; + DevConfig->Config.Clock[i].SDCLKout_FMT = 1; + DevConfig->Config.Clock[i].SDCLKout_POL = 0; + } + else + { + DevConfig->Config.Clock[i].DCLKout_Div = 0; + DevConfig->Config.Clock[i].CLKout_IDL = 0; + DevConfig->Config.Clock[i].CLKout_ODL = 0; + + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 5; + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 5; + + DevConfig->Config.Clock[i].DCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ALDY = 0; + + DevConfig->Config.Clock[i].SDCLKout_HS = 0; + DevConfig->Config.Clock[i].SDCLKout_DDLY = 0; + DevConfig->Config.Clock[i].SDCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_HS = 0; + + DevConfig->Config.Clock[i].SDCLK_ADLY = 0; + DevConfig->Config.Clock[i].SDCLKout_ADLY_EN = 0; + + DevConfig->Config.Clock[i].SDCLKout_PD = 1; + DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0; + DevConfig->Config.Clock[i].CLKout_PD = 1; + DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1; + DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1; + DevConfig->Config.Clock[i].DCLKout_HSg_PD = 1; + DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 1; + + DevConfig->Config.Clock[i].DCLKout_FMT = 0; + DevConfig->Config.Clock[i].DCLKout_POL = 0; + DevConfig->Config.Clock[i].SDCLKout_FMT = 0; + DevConfig->Config.Clock[i].SDCLKout_POL = 0; + } + + } + + LMK_ConfigCustomize(DevConfig); + + return XST_SUCCESS; +} + +__weak int LMK_ConfigCustomize(LMK_Config *DevConfig) +{ + UNUSED(DevConfig); + return XST_FAILURE; +} + +int LMK_Init(LMK_Config *DevConfig) +{ + int i; + uint8_t tmp; + uint8_t ld1, ld2; + //Unlock SPI Register + //LMK_WriteReg(DevConfig, 0x1FFD, 0); + //LMK_WriteReg(DevConfig, 0x1FFE, 0); + //LMK_WriteReg(DevConfig, 0x1FFF, 83); + LMK_RegUnlock(DevConfig); + + //Reset Register + LMK_WriteReg(DevConfig, 0x000, 0x80); + + //4-wire SPI + LMK_WriteReg(DevConfig, 0x000, 0x10); + + //Reserved Register + //LMK_WriteReg(DevConfig, 0x145, 0x7F); + //LMK_WriteReg(DevConfig, 0x171, 0xAA); + //LMK_WriteReg(DevConfig, 0x172, 0x02); + //LMK_WriteReg(DevConfig, 0x17C, 21); + //LMK_WriteReg(DevConfig, 0x17D, 51); + + //Sequence Program + for(i = 0; i < sizeof(DevConfig->Config); i++) + { + LMK_WriteReg(DevConfig, 0x100 + i, ((u8*)(&DevConfig->Config))[i]); + } + + tmp = 1; + while(tmp) + { + LMK_ReadReg(DevConfig, 0x182, &ld1); + LMK_ReadReg(DevConfig, 0x183, &ld2); + tmp = (ld1 & 0x02) & (ld2 & 0x02) == 0x02 ? 1 : 0; + } + + //Enable SYSREF + LMK_WriteReg(DevConfig, 0x140, 0xFB & ((u8*)(&DevConfig->Config))[0x040]); //SYSREF_PD = 0 + LMK_WriteReg(DevConfig, 0x143, 0x7F & ((u8*)(&DevConfig->Config))[0x043]); //SYSREF_CLR = 0 + /*LMK_WriteReg(DevConfig, 0x143, 0x80 | ((u8*)(&DevConfig->Config))[0x043]); //SYSREF_CLR = 1 + LMK_WriteReg(DevConfig, 0x144, 0x00); + LMK_WriteReg(DevConfig, 0x143, 0x20 | ((u8*)(&DevConfig->Config))[0x043]); //SYNC_POL = 1 + LMK_WriteReg(DevConfig, 0x143, 0xDF & ((u8*)(&DevConfig->Config))[0x043]); //SYNC_POL = 0 + LMK_WriteReg(DevConfig, 0x144, 0xFF); + LMK_WriteReg(DevConfig, 0x143, 0x7F & ((u8*)(&DevConfig->Config))[0x043]); //SYSREF_CLR = 0 + LMK_WriteReg(DevConfig, 0x139, ((u8*)(&DevConfig->Config))[0x039]); //SYSREF_MUX*/ + + LMK_RegLock(DevConfig); + + //Lock SPI Register + //LMK_WriteReg(DevConfig, 0x1FFD, 255); + //LMK_WriteReg(DevConfig, 0x1FFE, 255); + //LMK_WriteReg(DevConfig, 0x1FFF, 255); + return XST_SUCCESS; +} + +int LMK_StatusRead(LMK_Config *DevConfig) +{ + return XST_SUCCESS; +} + +int LMK_RegLock(LMK_Config *DevConfig) +{ + LMK_WriteReg(DevConfig, 0x1FFD, 255); + LMK_WriteReg(DevConfig, 0x1FFE, 255); + LMK_WriteReg(DevConfig, 0x1FFF, 255); + return XST_SUCCESS; +} + +int LMK_RegUnlock(LMK_Config *DevConfig) +{ + LMK_WriteReg(DevConfig, 0x1FFD, 0); + LMK_WriteReg(DevConfig, 0x1FFE, 0); + LMK_WriteReg(DevConfig, 0x1FFF, 83); + return XST_SUCCESS; +} + +#include "xspips.h" + +int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value) +{ + u8 buf[3]; + + buf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F); + buf[1] = RegisterAddress & 0xFF; + buf[2] = Value; + + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00); + XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, NULL, 3); + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F); + + return XST_SUCCESS; +} + +int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value) +{ + u8 buf[3]; + + buf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F); + buf[1] = RegisterAddress & 0xFF; + buf[2] = 0; + + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00); + XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, buf, 3); + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F); + + *Value = buf[2]; + + return XST_SUCCESS; +} diff --git a/LMK_ClockTree.h b/LMK_ClockTree.h new file mode 100644 index 0000000..daf1da8 --- /dev/null +++ b/LMK_ClockTree.h @@ -0,0 +1,296 @@ + /* + * LMK_ClockTree.h + * + * Created on: 2019��3��5�� + * Author: TiferKing + */ + +#ifndef SRC_LMK_CLOCKTREE_H_ +#define SRC_LMK_CLOCKTREE_H_ + +#include "xstatus.h" + +#include "ConfigCalculate.h" + +#define __weak __attribute__((weak)) +#define UNUSED(x) (void)x + +#define LMK_VCO0_RATE_L 2370000000 +#define LMK_VCO0_RATE_H 2630000000 +#define LMK_VCO1_RATE_L 2920000000 +#define LMK_VCO1_RATE_H 3080000000 +#define LMK_VCOX_RATE_L 122867712 +#define LMK_VCOX_RATE_H 122892288 +#define LMK_PLL1_LFBAND 80000 +#define LMK_PLL2_LFBAND 160000 + +// LMK Clock Channel Register Map +typedef struct LMK_ClockPair_Type +{ + u8 DCLKout_Div :4, + CLKout_IDL :1, + CLKout_ODL :1, + :1; + u8 DCLKout_DDLY_CNTL :4, + DCLKout_DDLY_CNTH :4; + u8 :8; + u8 DCLKout_MUX :2, + DCLKout_ADLY_MUX :1, + DCLKout_ALDY :5; + u8 SDCLKout_HS :1, + SDCLKout_DDLY :4, + SDCLKout_MUX :1, + DCLKout_HS :1, + :1; + u8 SDCLK_ADLY :4, + SDCLKout_ADLY_EN :1, + :3; + u8 SDCLKout_PD :1, + SDCLKout_DIS_MODE :2, + CLKout_PD :1, + DCLKout_ADLY_PD :1, + DCLKout_ADLYg_PD :1, + DCLKout_HSg_PD :1, + DCLKout_DDLY_PD :1; + u8 DCLKout_FMT :3, + DCLKout_POL :1, + SDCLKout_FMT :3, + SDCLKout_POL :1; +} LMK_ClockPair; + +// LMK Register Map +typedef struct LMK_RegMap_Type +{ + /******************************///Addr : 0x100 + LMK_ClockPair Clock[7]; + /******************************///Addr : 0x138 + u8 OSCout_FMT :4, + OSCout_MUX :1, + VCO_MUX :2, + :1; + u8 SYSREF_MUX :2, + SYSREF_CLKin0_MUX :1, + :5; + u8 SYSREF_DIVH :5, + :3; + u8 SYSREF_DIVL :8; + u8 SYSREF_DDLYH :5, + :3; + u8 SYSREF_DDLYL :8; + u8 SYSREF_PULSE_CNT :2, + :6; + u8 FB_MUX_EN :1, + FB_MUX :2, + PLL1_NCLK_MUX :1, + PLL2_NCLK_MUX :1, + :3; + /******************************///Addr : 0x140 + u8 SYSREF_PLSR_PD :1, + SYSREF_DDLY_PD :1, + SYSREF_PD :1, + SYSREF_GBL_PD :1, + OSCin_PD :1, + VCO_PD :1, + VCO_LDO_PD :1, + PLL1_PD :1; + u8 DDLYd0_EN :1, + DDLYd2_EN :1, + DDLYd4_EN :1, + DDLYd6_EN :1, + DDLYd8_EN :1, + DDLYd10_EN :1, + DDLYd12_EN :1, + DDLYd0_SYSREF_EN :1; + u8 DDLYd_STEP_CNT :4, + :4; + u8 SYNC_MODE :2, + SYNC_PLL1_DLD :1, + SYNC_PLL2_DLD :1, + SYNC_EN :1, + SYNC_POL :1, + SYNC_1SHOT_EN :1, + SYSREF_CLR :1; + u8 SYNC_DIS0 :1, + SYNC_DIS2 :1, + SYNC_DIS4 :1, + SYNC_DIS6 :1, + SYNC_DIS8 :1, + SYNC_DIS10 :1, + SYNC_DIS12 :1, + SYNC_DISSYSREF :1; + u8 Fixed_0 :8; //Fixed 0x7F + u8 CLKin0_TYPE :1, + CLKin1_TYPE :1, + CLKin2_TYPE :1, + CLKin0_EN :1, + CLKin1_EN :1, + CLKin2_EN :1, + :2; + u8 CLKin0_OUT_MUX :2, + CLKin1_OUT_MUX :2, + CLKin_SEL_MODE :3, + CLKin_SEL_POL :1; + u8 CLKin_SEL0_TYPE :3, + CLKin_SEL0_MUX :3, + :2; + u8 CLKin_SEL1_TYPE :3, + CLKin_SEL1_MUX :3, + SDIO_RDBK_TYPE :1, + :1; + u8 RESET_TYPE :3, + RESET_MUX :3, + :2; + u8 MAN_DACH :2, + MAN_DAC_EN :1, + HOLDOVER_FORCE :1, + TRACK_EN :1, + LOS_EN :1, + LOS_TIMEOUT :2; + u8 MAN_DACL :8; + u8 DAC_TRIP_LOW :6, + :2; + u8 DAC_TRIP_HIGH :6, + DAC_CLK_MULT :2; + u8 DAC_CLK_CNTR :8; + /******************************///Addr : 0x150 + u8 HOLDOVER_EN :1, + HOLDOVER_HITLESS_SW :1, + HOLDOVER_VTUNE_DET :1, + HOLDOVER_LOS_DET :1, + HOLDOVER_PLL1_DET :1, + :1, + CLKin_OVERRIDE :1, + :1; + u8 HOLDOVER_DLD_CNTH :6, + :2; + u8 HOLDOVER_DLD_CNTL :8; + u8 CLKin0_RH :6, + :2; + u8 CLKin0_RL :8; + u8 CLKin1_RH :6, + :2; + u8 CLKin1_RL :8; + u8 CLKin2_RH :6, + :2; + u8 CLKin2_RL :8; + u8 PLL1_NH :6, + :2; + u8 PLL1_NL :8; + u8 PLL1_CP_GAIN :4, + PLL1_CP_POL :1, + PLL1_CP_TRI :1, + PLL1_WND_SIZE :2; + u8 PLL1_DLD_CNTH :6, + :2; + u8 PLL1_DLD_CNTL :8; + u8 PLL1_N_DLY :3, + PLL1_R_DLY :3, + :2; + u8 PLL1_LD_TYPE :3, + PLL1_LD_MUX :5; + /******************************///Addr : 0x160 + u8 PLL2_RH :4, + :4; + u8 PLL2_RL :8; + u8 PLL2_REF_2X_EN :1, + PLL2_XTAL_EN :1, + OSCin_FREQ :3, + PLL2_P :3; + u8 PLL2_N_CALH :2, + :6; + u8 PLL2_N_CALM :8; + u8 PLL2_N_CALL :8; + u8 PLL2_NH :2, + PLL2_FCAL_DIS :1, + :5; + u8 PLL2_NM :8; + u8 PLL2_NL :8; + u8 Fixed_1 :1, //Fixed 0x01 + PLL2_CP_TRI :1, + PLL2_CP_POL :1, + PLL2_CP_GAIN :2, + PLL2_WND_SIZE :2, + :1; + u8 PLL2_DLD_CNTH :6, + SYSREF_REQ_EN :1, + :1; + u8 PLL2_DLD_CNTL :8; + u8 PLL2_LF_R3 :3, + PLL2_LF_R4 :3, + :2; + u8 PLL2_LF_C3 :4, + PLL2_LF_C4 :4; + u8 PLL2_LD_TYPE :3, + PLL2_LD_MUX :5; + u8 :8; + /******************************///Addr : 0x170 + u8 :8; + u8 Fixed_2 :8; //Fixed 0xAA + u8 Fixed_3 :8; //Fixed 0x02 + u8 :5, + PLL2_PD :1, + PLL2_PRE_PD :1, + :1; + u8 VCO1_DIV :5, + :3; +} LMK_RegMap; + +// LMK Reg Read Back Map +typedef struct LMK_ReadBack_Type +{ + //Addr : 0x182 + u8 CLR_PLL1_LD_LOST :1, + RB_PLL1_LD :1, + RB_PLL1_LD_LOST :1, + :5; + u8 CLR_PLL2_LD_LOST :1, + RB_PLL2_LD :1, + RB_PLL2_LD_LOST :1, + :5; + u8 RB_CLKin0_LOS :1, + RB_CLKin1_LOS :1, + :1, + RB_CLKin0_SEL :1, + RB_CLKin1_SEL :1, + RB_CLKin2_SEL :1, + RB_DAC_VALUEH :2; + u8 RB_DAC_VALUEL :8; + u8 :8; + u8 :8; + u8 :4, + RB_HOLDOVER :1, + :3; +} LMK_ReadBack; + + +typedef struct LMK_Config_Type +{ + void *InterfaceInst; + LMK_RegMap Config; + LMK_ReadBack Status; +} LMK_Config; + +typedef struct LMK_Config_Simple_Type +{ + void *InterfaceInst; + //Unit Hz; + u64 RefClockRate; + u64 VCOXClockRate; + u64 DClockRate[7]; + u64 SYSREFRate; +} LMK_Simple; + + +int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig); +int LMK_ConfigCustomize(LMK_Config *DevConfig); +int LMK_Init(LMK_Config *DevConfig); +int LMK_StatusRead(LMK_Config *DevConfig); +int LMK_RegLock(LMK_Config *DevConfig); +int LMK_RegUnlock(LMK_Config *DevConfig); + +int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value); +int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value); + + + +#endif /* SRC_LMK_CLOCKTREE_H_ */