From 8f2f72188b57981b67fa0957aecf69e7245804ed Mon Sep 17 00:00:00 2001 From: Tifer King Date: Sat, 18 Jan 2025 02:36:33 +0800 Subject: [PATCH] Add preset configuration --- LMK_ClockTree.c | 264 +++++++++++++++++++---------------------- LMK_ClockTree.h | 39 +++++++ LMK_Preset.c | 304 ++++++++++++++++++++++++++++++++++++++++++++++++ LMK_Preset.h | 19 +++ 4 files changed, 484 insertions(+), 142 deletions(-) create mode 100644 LMK_Preset.c create mode 100644 LMK_Preset.h diff --git a/LMK_ClockTree.c b/LMK_ClockTree.c index 2630d18..73020c2 100644 --- a/LMK_ClockTree.c +++ b/LMK_ClockTree.c @@ -7,31 +7,19 @@ #include "LMK_ClockTree.h" -__weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) +__weak int LMK_CalPLL1CommonRate(LMK_Simple *SimpleConfig) { - int i; + SimpleConfig->Generated.PLL1CommonRate = GreatestCommonDivisor(SimpleConfig->RefClockRate, SimpleConfig->VCOXClockRate); + LMK_AssertInValid(SimpleConfig->Generated.PLL1CommonRate); + return LMK_SUCCESS; +} + +__weak int LMK_CalPLL2CommonRate(LMK_Simple *SimpleConfig) +{ + u64 PLL2CommonRate; u64 ChMaxRate; u64 VCORate; - u64 PLL1CommonRate; - u64 PLL2CommonRate; u64 RootDiv; - //u64 PLLDiv; - u8 VCOSelect; - - DevConfig->InterfaceInst = SimpleConfig->InterfaceInst; - - - PLL1CommonRate = GreatestCommonDivisor(SimpleConfig->RefClockRate, SimpleConfig->VCOXClockRate); - /*if(PLL1CommonRate > LMK_PLL1_LFBAND) - { - PLLDiv = PLL1CommonRate / LMK_PLL1_LFBAND; - PLL1CommonRate /= PLLDiv + 1; - }*/ - if(PLL1CommonRate < 1000) - { - return XST_FAILURE; - } - ChMaxRate = 0; for(i = 0; i < 7; i++) { @@ -47,62 +35,67 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) } } } - - if(ChMaxRate == 0) - { - return XST_FAILURE; - } - + LMK_AssertZero(ChMaxRate); if((LMK_VCO0_RATE_L / ChMaxRate) < (LMK_VCO0_RATE_H / ChMaxRate)) { RootDiv = (LMK_VCO0_RATE_L / ChMaxRate) + 1; - VCORate = RootDiv * ChMaxRate; - VCOSelect = 0; + SimpleConfig->Generated.VCORate = RootDiv * ChMaxRate; + SimpleConfig->Generated.VCOSelect = 0; } else if((LMK_VCO1_RATE_L / ChMaxRate) < (LMK_VCO1_RATE_H / ChMaxRate)) { RootDiv = (LMK_VCO1_RATE_L / ChMaxRate) + 1; - VCORate = RootDiv * ChMaxRate; - VCOSelect = 1; + SimpleConfig->Generated.VCORate = RootDiv * ChMaxRate; + SimpleConfig->Generated.VCOSelect = 1; } else { - return XST_FAILURE; + return LMK_FAILURE; } - PLL2CommonRate = GreatestCommonDivisor(VCORate, SimpleConfig->VCOXClockRate * 2) / 2; - /*if(PLL2CommonRate > LMK_PLL2_LFBAND) - { - PLLDiv = PLL2CommonRate / LMK_PLL2_LFBAND; - PLL2CommonRate /= PLLDiv + 1; - }*/ - if(PLL2CommonRate < 1000) - { - return XST_FAILURE; - } + LMK_AssertInValid(PLL2CommonRate); + SimpleConfig->Generated.PLL2CommonRate = PLL2CommonRate; + return LMK_SUCCESS; +} +__weak int LMK_CalRegister(LMK_Simple *SimpleConfig) +{ + LMK_AssertZero(SimpleConfig->SYSREFRate); + LMK_AssertZero(SimpleConfig->Generated.PLL1CommonRate); + LMK_AssertZero(SimpleConfig->Generated.PLL2CommonRate); + SimpleConfig->Generated.SYSREF_DIV = SimpleConfig->Generated.VCORate / SimpleConfig->SYSREFRate; + SimpleConfig->Generated.CLKin_R = SimpleConfig->Generated.RefClockRate / SimpleConfig->Generated.PLL1CommonRate; + SimpleConfig->Generated.PLL1_N = SimpleConfig->Generated.VCOXClockRate / SimpleConfig->Generated.PLL1CommonRate; + SimpleConfig->Generated.PLL2_R = SimpleConfig->Generated.VCOXClockRate / SimpleConfig->Generated.PLL2CommonRate; + SimpleConfig->Generated.PLL2_N = SimpleConfig->Generated.VCORate / SimpleConfig->Generated.PLL2CommonRate / 2; + return LMK_SUCCESS; +} + +__weak int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) +{ + int i; // Fixed Register Set - DevConfig->Config.Fixed_0 = 0x7F; - DevConfig->Config.Fixed_1 = 0x01; - DevConfig->Config.Fixed_2 = 0xAA; - DevConfig->Config.Fixed_3 = 0x02; + DevConfig->Config.Fixed_0 = 0x7F; + DevConfig->Config.Fixed_1 = 0x01; + DevConfig->Config.Fixed_2 = 0xAA; + DevConfig->Config.Fixed_3 = 0x02; // Calculate Register Value - DevConfig->Config.OSCout_FMT = 0x00; + DevConfig->Config.OSCout_FMT = 4; DevConfig->Config.OSCout_MUX = 0; - DevConfig->Config.VCO_MUX = VCOSelect; + DevConfig->Config.VCO_MUX = 0; - DevConfig->Config.SYSREF_MUX = 3; + DevConfig->Config.SYSREF_MUX = 0; DevConfig->Config.SYSREF_CLKin0_MUX = 0; - DevConfig->Config.SYSREF_DIVH = (VCORate / SimpleConfig->SYSREFRate) >> 8; - DevConfig->Config.SYSREF_DIVL = (VCORate / SimpleConfig->SYSREFRate) & 0xFF; + DevConfig->Config.SYSREF_DIVH = 12; + DevConfig->Config.SYSREF_DIVL = 0; DevConfig->Config.SYSREF_DDLYH = 0; DevConfig->Config.SYSREF_DDLYL = 8; - DevConfig->Config.SYSREF_PULSE_CNT = 0x03; + DevConfig->Config.SYSREF_PULSE_CNT = 3; DevConfig->Config.FB_MUX_EN = 0; DevConfig->Config.FB_MUX = 0; @@ -110,7 +103,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.PLL2_NCLK_MUX = 0; DevConfig->Config.SYSREF_PLSR_PD = 1; - DevConfig->Config.SYSREF_DDLY_PD = 0; + DevConfig->Config.SYSREF_DDLY_PD = 1; DevConfig->Config.SYSREF_PD = 1; DevConfig->Config.SYSREF_GBL_PD = 0; DevConfig->Config.OSCin_PD = 0; @@ -137,33 +130,33 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.SYNC_1SHOT_EN = 0; DevConfig->Config.SYSREF_CLR = 1; - DevConfig->Config.SYNC_DIS0 = 1; - DevConfig->Config.SYNC_DIS2 = 1; - DevConfig->Config.SYNC_DIS4 = 1; - DevConfig->Config.SYNC_DIS6 = 1; - DevConfig->Config.SYNC_DIS8 = 1; - DevConfig->Config.SYNC_DIS10 = 1; - DevConfig->Config.SYNC_DIS12 = 1; - DevConfig->Config.SYNC_DISSYSREF = 1; + DevConfig->Config.SYNC_DIS0 = 0; + DevConfig->Config.SYNC_DIS2 = 0; + DevConfig->Config.SYNC_DIS4 = 0; + DevConfig->Config.SYNC_DIS6 = 0; + DevConfig->Config.SYNC_DIS8 = 0; + DevConfig->Config.SYNC_DIS10 = 0; + DevConfig->Config.SYNC_DIS12 = 0; + DevConfig->Config.SYNC_DISSYSREF = 0; DevConfig->Config.CLKin0_TYPE = 0; DevConfig->Config.CLKin1_TYPE = 0; DevConfig->Config.CLKin2_TYPE = 0; - DevConfig->Config.CLKin0_EN = 0; - DevConfig->Config.CLKin1_EN = 0; + DevConfig->Config.CLKin0_EN = 1; + DevConfig->Config.CLKin1_EN = 1; DevConfig->Config.CLKin2_EN = 0; - DevConfig->Config.CLKin0_OUT_MUX = 3; - DevConfig->Config.CLKin1_OUT_MUX = 3; - DevConfig->Config.CLKin_SEL_MODE = 2; + DevConfig->Config.CLKin0_OUT_MUX = 2; + DevConfig->Config.CLKin1_OUT_MUX = 2; + DevConfig->Config.CLKin_SEL_MODE = 3; DevConfig->Config.CLKin_SEL_POL = 0; - DevConfig->Config.CLKin_SEL0_TYPE = 3; - DevConfig->Config.CLKin_SEL0_MUX = 6; + DevConfig->Config.CLKin_SEL0_TYPE = 2; + DevConfig->Config.CLKin_SEL0_MUX = 0; - DevConfig->Config.CLKin_SEL1_TYPE = 0; + DevConfig->Config.CLKin_SEL1_TYPE = 2; DevConfig->Config.CLKin_SEL1_MUX = 0; - DevConfig->Config.SDIO_RDBK_TYPE = 0; + DevConfig->Config.SDIO_RDBK_TYPE = 1; DevConfig->Config.RESET_TYPE = 2; DevConfig->Config.RESET_MUX = 0; @@ -182,7 +175,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.DAC_TRIP_HIGH = 0; DevConfig->Config.DAC_CLK_MULT = 0; - DevConfig->Config.DAC_CLK_CNTR = 0x7F; + DevConfig->Config.DAC_CLK_CNTR = 127; DevConfig->Config.HOLDOVER_EN = 1; DevConfig->Config.HOLDOVER_HITLESS_SW = 1; @@ -198,13 +191,13 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.CLKin0_RL = 120; DevConfig->Config.CLKin1_RH = 0; DevConfig->Config.CLKin1_RL = 150; - DevConfig->Config.CLKin2_RH = (SimpleConfig->RefClockRate / PLL1CommonRate) >> 8; - DevConfig->Config.CLKin2_RL = (SimpleConfig->RefClockRate / PLL1CommonRate) & 0xFF; + DevConfig->Config.CLKin2_RH = 0; + DevConfig->Config.CLKin2_RL = 150; - DevConfig->Config.PLL1_NH = (SimpleConfig->VCOXClockRate / PLL1CommonRate) >> 8; - DevConfig->Config.PLL1_NL = ((SimpleConfig->VCOXClockRate / PLL1CommonRate) & 0xFF); + DevConfig->Config.PLL1_NH = 0; + DevConfig->Config.PLL1_NL = 120; - DevConfig->Config.PLL1_CP_GAIN = 15; + DevConfig->Config.PLL1_CP_GAIN = 4; DevConfig->Config.PLL1_CP_POL = 1; DevConfig->Config.PLL1_CP_TRI = 0; DevConfig->Config.PLL1_WND_SIZE = 3; @@ -215,25 +208,25 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.PLL1_N_DLY = 0; DevConfig->Config.PLL1_R_DLY = 0; - DevConfig->Config.PLL1_LD_TYPE = 3; + DevConfig->Config.PLL1_LD_TYPE = 6; DevConfig->Config.PLL1_LD_MUX = 1; - DevConfig->Config.PLL2_RH = (SimpleConfig->VCOXClockRate / PLL2CommonRate) >> 8; - DevConfig->Config.PLL2_RL = (SimpleConfig->VCOXClockRate / PLL2CommonRate) & 0xFF; + DevConfig->Config.PLL2_RH = 0; + DevConfig->Config.PLL2_RL = 2; - DevConfig->Config.PLL2_REF_2X_EN = 0; + DevConfig->Config.PLL2_REF_2X_EN = 1; DevConfig->Config.PLL2_XTAL_EN = 0; - DevConfig->Config.OSCin_FREQ = 4; + DevConfig->Config.OSCin_FREQ = 7; DevConfig->Config.PLL2_P = 2; DevConfig->Config.PLL2_N_CALH = 0; DevConfig->Config.PLL2_N_CALM = 0; DevConfig->Config.PLL2_N_CALL = 12; - DevConfig->Config.PLL2_NH = ((VCORate / PLL2CommonRate / 2) >> 16) & 0xFF; + DevConfig->Config.PLL2_NH = 0; DevConfig->Config.PLL2_FCAL_DIS = 0; - DevConfig->Config.PLL2_NM = ((VCORate / PLL2CommonRate / 2) >> 8) & 0xFF; - DevConfig->Config.PLL2_NL = (VCORate / PLL2CommonRate / 2) & 0xFF; + DevConfig->Config.PLL2_NM = 0; + DevConfig->Config.PLL2_NL = 12; DevConfig->Config.PLL2_CP_TRI = 0; DevConfig->Config.PLL2_CP_POL = 0; @@ -241,7 +234,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.PLL2_WND_SIZE = 2; DevConfig->Config.PLL2_DLD_CNTH = 32; - DevConfig->Config.SYSREF_REQ_EN = 1; + DevConfig->Config.SYSREF_REQ_EN = 0; DevConfig->Config.PLL2_DLD_CNTL = 0; DevConfig->Config.PLL2_LF_R3 = 0; @@ -249,7 +242,7 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.PLL2_LF_C3 = 0; DevConfig->Config.PLL2_LF_C4 = 0; - DevConfig->Config.PLL2_LD_TYPE = 3; + DevConfig->Config.PLL2_LD_TYPE = 6; DevConfig->Config.PLL2_LD_MUX = 2; DevConfig->Config.PLL2_PD = 0; @@ -327,18 +320,36 @@ __weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) DevConfig->Config.Clock[i].SDCLKout_FMT = 0; DevConfig->Config.Clock[i].SDCLKout_POL = 0; } - } - - LMK_ConfigCustomize(DevConfig); - - return XST_SUCCESS; + return LMK_SUCCESS; } -__weak int LMK_ConfigCustomize(LMK_Config *DevConfig) +__weak int LMK_ConfigPreset(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) { UNUSED(DevConfig); - return XST_FAILURE; + UNUSED(SimpleConfig); + return LMK_SUCCESS; +} + +__weak int LMK_ConfigCustomize(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) +{ + UNUSED(DevConfig); + UNUSED(SimpleConfig); + return LMK_SUCCESS; +} + +__weak int LMK_ConfigMake(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) +{ + LMK_AssertZero(SimpleConfig->InterfaceInst); + LMK_AssertFailure(LMK_CalPLL1CommonRate(SimpleConfig)); + LMK_AssertFailure(LMK_CalPLL2CommonRate(SimpleConfig)); + LMK_AssertFailure(LMK_CalRegister(SimpleConfig)); + LMK_AssertFailure(LMK_ConfigSetRegister(DevConfig, SimpleConfig)); + LMK_AssertFailure(LMK_ConfigPreset(DevConfig, SimpleConfig)); + LMK_AssertFailure(LMK_ConfigCustomize(DevConfig, SimpleConfig)); + DevConfig->InterfaceInst = SimpleConfig->InterfaceInst; + + return LMK_SUCCESS; } int LMK_Init(LMK_Config *DevConfig) @@ -347,25 +358,17 @@ int LMK_Init(LMK_Config *DevConfig) uint8_t tmp; uint8_t ld1, ld2; //Unlock SPI Register - //LMK_WriteReg(DevConfig, 0x1FFD, 0); - //LMK_WriteReg(DevConfig, 0x1FFE, 0); - //LMK_WriteReg(DevConfig, 0x1FFF, 83); LMK_RegUnlock(DevConfig); //Reset Register LMK_WriteReg(DevConfig, 0x000, 0x80); - //4-wire SPI + //Enable 4-wire SPI LMK_WriteReg(DevConfig, 0x000, 0x10); - //Reserved Register - //LMK_WriteReg(DevConfig, 0x145, 0x7F); - //LMK_WriteReg(DevConfig, 0x171, 0xAA); - //LMK_WriteReg(DevConfig, 0x172, 0x02); - //LMK_WriteReg(DevConfig, 0x17C, 21); - //LMK_WriteReg(DevConfig, 0x17D, 51); - //Sequence Program + LMK_WriteReg(DevConfig, 0x17C, 21); + LMK_WriteReg(DevConfig, 0x17D, 51); for(i = 0; i < sizeof(DevConfig->Config); i++) { LMK_WriteReg(DevConfig, 0x100 + i, ((u8*)(&DevConfig->Config))[i]); @@ -391,17 +394,12 @@ int LMK_Init(LMK_Config *DevConfig) LMK_WriteReg(DevConfig, 0x139, ((u8*)(&DevConfig->Config))[0x039]); //SYSREF_MUX*/ LMK_RegLock(DevConfig); - - //Lock SPI Register - //LMK_WriteReg(DevConfig, 0x1FFD, 255); - //LMK_WriteReg(DevConfig, 0x1FFE, 255); - //LMK_WriteReg(DevConfig, 0x1FFF, 255); - return XST_SUCCESS; + return LMK_SUCCESS; } -int LMK_StatusRead(LMK_Config *DevConfig) +__weak int LMK_StatusRead(LMK_Config *DevConfig) { - return XST_SUCCESS; + return LMK_SUCCESS; } int LMK_RegLock(LMK_Config *DevConfig) @@ -409,7 +407,7 @@ int LMK_RegLock(LMK_Config *DevConfig) LMK_WriteReg(DevConfig, 0x1FFD, 255); LMK_WriteReg(DevConfig, 0x1FFE, 255); LMK_WriteReg(DevConfig, 0x1FFF, 255); - return XST_SUCCESS; + return LMK_SUCCESS; } int LMK_RegUnlock(LMK_Config *DevConfig) @@ -417,39 +415,21 @@ int LMK_RegUnlock(LMK_Config *DevConfig) LMK_WriteReg(DevConfig, 0x1FFD, 0); LMK_WriteReg(DevConfig, 0x1FFE, 0); LMK_WriteReg(DevConfig, 0x1FFF, 83); - return XST_SUCCESS; + return LMK_SUCCESS; } -#include "xspips.h" - -int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value) +__weak int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value) { - u8 buf[3]; - - buf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F); - buf[1] = RegisterAddress & 0xFF; - buf[2] = Value; - - XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00); - XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, NULL, 3); - XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F); - - return XST_SUCCESS; + UNUSED(DevConfig); + UNUSED(RegisterAddress); + UNUSED(Value); + return LMK_SUCCESS; } -int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value) +__weak int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value) { - u8 buf[3]; - - buf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F); - buf[1] = RegisterAddress & 0xFF; - buf[2] = 0; - - XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00); - XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, buf, 3); - XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F); - - *Value = buf[2]; - - return XST_SUCCESS; + UNUSED(DevConfig); + UNUSED(RegisterAddress); + UNUSED(Value); + return LMK_SUCCESS; } diff --git a/LMK_ClockTree.h b/LMK_ClockTree.h index 9976f87..fef644b 100644 --- a/LMK_ClockTree.h +++ b/LMK_ClockTree.h @@ -14,6 +14,29 @@ #define __weak __attribute__((weak)) #define UNUSED(x) (void)x +#define LMK_SUCCESS 0 +#define LMK_FAILURE 1 + +#define LMK_AssertInValid(Expression) \ +{ \ + if ((Expression) < 1000) { \ + return LMK_FAILURE; \ + } \ +} + +#define LMK_AssertZero(Expression) \ +{ \ + if ((Expression) == 0) { \ + return LMK_FAILURE; \ + } \ +} + +#define LMK_AssertFailure(Expression) \ +{ \ + if ((Expression) != LMK_SUCCESS) { \ + return LMK_FAILURE; \ + } \ +} #define LMK_VCO0_RATE_L 2370000000 #define LMK_VCO0_RATE_H 2630000000 @@ -270,6 +293,19 @@ typedef struct LMK_Config_Type LMK_ReadBack Status; } LMK_Config; +typedef struct LMK_Config_Generated_Type +{ + u64 PLL1CommonRate; + u64 PLL2CommonRate; + u64 VCORate; + u16 SYSREF_DIV; + u16 CLKin_R; + u16 PLL1_N; + u16 PLL2_R; + u32 PLL2_N; + u8 VCOSelect; +} LMK_Generated; + typedef struct LMK_Config_Simple_Type { void *InterfaceInst; @@ -278,6 +314,9 @@ typedef struct LMK_Config_Simple_Type u64 VCOXClockRate; u64 DClockRate[7]; u64 SYSREFRate; + + //Generated config + LMK_Generated Generated; } LMK_Simple; diff --git a/LMK_Preset.c b/LMK_Preset.c new file mode 100644 index 0000000..eeb531d --- /dev/null +++ b/LMK_Preset.c @@ -0,0 +1,304 @@ +/* + * LMK_Preset.c + * + * Created on: 2025.01.16 + * Author: TiferKing + */ + +#include "LMK_Preset.h" + +#ifdef LMK_PRESET_NONE +#endif //LMK_PRESET_NONE + +#ifdef LMK_PRESET_IW_RFSOC_2T2R_INTERNAL + +#include "xspips.h" + +__weak int LMK_ConfigSetRegister(LMK_Config *DevConfig, LMK_Simple *SimpleConfig) +{ + int i; + // Fixed Register Set + DevConfig->Config.Fixed_0 = 0x7F; + DevConfig->Config.Fixed_1 = 0x01; + DevConfig->Config.Fixed_2 = 0xAA; + DevConfig->Config.Fixed_3 = 0x02; + + // Calculate Register Value + DevConfig->Config.OSCout_FMT = 0x00; + DevConfig->Config.OSCout_MUX = 0; + DevConfig->Config.VCO_MUX = VCOSelect; + + DevConfig->Config.SYSREF_MUX = 3; + DevConfig->Config.SYSREF_CLKin0_MUX = 0; + + DevConfig->Config.SYSREF_DIVH = (VCORate / SimpleConfig->SYSREFRate) >> 8; + DevConfig->Config.SYSREF_DIVL = (VCORate / SimpleConfig->SYSREFRate) & 0xFF; + + DevConfig->Config.SYSREF_DDLYH = 0; + DevConfig->Config.SYSREF_DDLYL = 8; + + DevConfig->Config.SYSREF_PULSE_CNT = 0x03; + + DevConfig->Config.FB_MUX_EN = 0; + DevConfig->Config.FB_MUX = 0; + DevConfig->Config.PLL1_NCLK_MUX = 0; + DevConfig->Config.PLL2_NCLK_MUX = 0; + + DevConfig->Config.SYSREF_PLSR_PD = 1; + DevConfig->Config.SYSREF_DDLY_PD = 0; + DevConfig->Config.SYSREF_PD = 1; + DevConfig->Config.SYSREF_GBL_PD = 0; + DevConfig->Config.OSCin_PD = 0; + DevConfig->Config.VCO_PD = 0; + DevConfig->Config.VCO_LDO_PD = 0; + DevConfig->Config.PLL1_PD = 0; + + DevConfig->Config.DDLYd0_EN = 0; + DevConfig->Config.DDLYd2_EN = 0; + DevConfig->Config.DDLYd4_EN = 0; + DevConfig->Config.DDLYd6_EN = 0; + DevConfig->Config.DDLYd8_EN = 0; + DevConfig->Config.DDLYd10_EN = 0; + DevConfig->Config.DDLYd12_EN = 0; + DevConfig->Config.DDLYd0_SYSREF_EN = 0; + + DevConfig->Config.DDLYd_STEP_CNT = 0; + + DevConfig->Config.SYNC_MODE = 1; + DevConfig->Config.SYNC_PLL1_DLD = 0; + DevConfig->Config.SYNC_PLL2_DLD = 0; + DevConfig->Config.SYNC_EN = 1; + DevConfig->Config.SYNC_POL = 0; + DevConfig->Config.SYNC_1SHOT_EN = 0; + DevConfig->Config.SYSREF_CLR = 1; + + DevConfig->Config.SYNC_DIS0 = 1; + DevConfig->Config.SYNC_DIS2 = 1; + DevConfig->Config.SYNC_DIS4 = 1; + DevConfig->Config.SYNC_DIS6 = 1; + DevConfig->Config.SYNC_DIS8 = 1; + DevConfig->Config.SYNC_DIS10 = 1; + DevConfig->Config.SYNC_DIS12 = 1; + DevConfig->Config.SYNC_DISSYSREF = 1; + + DevConfig->Config.CLKin0_TYPE = 0; + DevConfig->Config.CLKin1_TYPE = 0; + DevConfig->Config.CLKin2_TYPE = 0; + DevConfig->Config.CLKin0_EN = 0; + DevConfig->Config.CLKin1_EN = 0; + DevConfig->Config.CLKin2_EN = 0; + + DevConfig->Config.CLKin0_OUT_MUX = 3; + DevConfig->Config.CLKin1_OUT_MUX = 3; + DevConfig->Config.CLKin_SEL_MODE = 2; + DevConfig->Config.CLKin_SEL_POL = 0; + + DevConfig->Config.CLKin_SEL0_TYPE = 3; + DevConfig->Config.CLKin_SEL0_MUX = 6; + + DevConfig->Config.CLKin_SEL1_TYPE = 0; + DevConfig->Config.CLKin_SEL1_MUX = 0; + DevConfig->Config.SDIO_RDBK_TYPE = 0; + + DevConfig->Config.RESET_TYPE = 2; + DevConfig->Config.RESET_MUX = 0; + + DevConfig->Config.MAN_DACH = 2; + DevConfig->Config.MAN_DAC_EN = 1; + DevConfig->Config.HOLDOVER_FORCE = 0; + DevConfig->Config.TRACK_EN = 1; + DevConfig->Config.LOS_EN = 0; + DevConfig->Config.LOS_TIMEOUT = 0; + + DevConfig->Config.MAN_DACL = 0; + + DevConfig->Config.DAC_TRIP_LOW = 0; + + DevConfig->Config.DAC_TRIP_HIGH = 0; + DevConfig->Config.DAC_CLK_MULT = 0; + + DevConfig->Config.DAC_CLK_CNTR = 0x7F; + + DevConfig->Config.HOLDOVER_EN = 1; + DevConfig->Config.HOLDOVER_HITLESS_SW = 1; + DevConfig->Config.HOLDOVER_VTUNE_DET = 0; + DevConfig->Config.HOLDOVER_LOS_DET = 0; + DevConfig->Config.HOLDOVER_PLL1_DET = 0; + DevConfig->Config.CLKin_OVERRIDE = 0; + + DevConfig->Config.HOLDOVER_DLD_CNTH = 2; + + DevConfig->Config.HOLDOVER_DLD_CNTL = 0; + DevConfig->Config.CLKin0_RH = 0; + DevConfig->Config.CLKin0_RL = 120; + DevConfig->Config.CLKin1_RH = 0; + DevConfig->Config.CLKin1_RL = 150; + DevConfig->Config.CLKin2_RH = (SimpleConfig->RefClockRate / PLL1CommonRate) >> 8; + DevConfig->Config.CLKin2_RL = (SimpleConfig->RefClockRate / PLL1CommonRate) & 0xFF; + + DevConfig->Config.PLL1_NH = (SimpleConfig->VCOXClockRate / PLL1CommonRate) >> 8; + DevConfig->Config.PLL1_NL = ((SimpleConfig->VCOXClockRate / PLL1CommonRate) & 0xFF); + + DevConfig->Config.PLL1_CP_GAIN = 15; + DevConfig->Config.PLL1_CP_POL = 1; + DevConfig->Config.PLL1_CP_TRI = 0; + DevConfig->Config.PLL1_WND_SIZE = 3; + + DevConfig->Config.PLL1_DLD_CNTH = 32; + DevConfig->Config.PLL1_DLD_CNTL = 0; + + DevConfig->Config.PLL1_N_DLY = 0; + DevConfig->Config.PLL1_R_DLY = 0; + + DevConfig->Config.PLL1_LD_TYPE = 3; + DevConfig->Config.PLL1_LD_MUX = 1; + + DevConfig->Config.PLL2_RH = (SimpleConfig->VCOXClockRate / PLL2CommonRate) >> 8; + DevConfig->Config.PLL2_RL = (SimpleConfig->VCOXClockRate / PLL2CommonRate) & 0xFF; + + DevConfig->Config.PLL2_REF_2X_EN = 0; + DevConfig->Config.PLL2_XTAL_EN = 0; + DevConfig->Config.OSCin_FREQ = 4; + DevConfig->Config.PLL2_P = 2; + + DevConfig->Config.PLL2_N_CALH = 0; + DevConfig->Config.PLL2_N_CALM = 0; + DevConfig->Config.PLL2_N_CALL = 12; + + DevConfig->Config.PLL2_NH = ((VCORate / PLL2CommonRate / 2) >> 16) & 0xFF; + DevConfig->Config.PLL2_FCAL_DIS = 0; + DevConfig->Config.PLL2_NM = ((VCORate / PLL2CommonRate / 2) >> 8) & 0xFF; + DevConfig->Config.PLL2_NL = (VCORate / PLL2CommonRate / 2) & 0xFF; + + DevConfig->Config.PLL2_CP_TRI = 0; + DevConfig->Config.PLL2_CP_POL = 0; + DevConfig->Config.PLL2_CP_GAIN = 3; + DevConfig->Config.PLL2_WND_SIZE = 2; + + DevConfig->Config.PLL2_DLD_CNTH = 32; + DevConfig->Config.SYSREF_REQ_EN = 1; + DevConfig->Config.PLL2_DLD_CNTL = 0; + + DevConfig->Config.PLL2_LF_R3 = 0; + DevConfig->Config.PLL2_LF_R4 = 0; + + DevConfig->Config.PLL2_LF_C3 = 0; + DevConfig->Config.PLL2_LF_C4 = 0; + DevConfig->Config.PLL2_LD_TYPE = 3; + DevConfig->Config.PLL2_LD_MUX = 2; + + DevConfig->Config.PLL2_PD = 0; + DevConfig->Config.PLL2_PRE_PD = 0; + + DevConfig->Config.VCO1_DIV = 0; + + for(i = 0; i < 7; i++) + { + if(VCORate / SimpleConfig->DClockRate[i] != 0) + { + DevConfig->Config.Clock[i].DCLKout_Div = VCORate / SimpleConfig->DClockRate[i]; + DevConfig->Config.Clock[i].CLKout_IDL = 0; + DevConfig->Config.Clock[i].CLKout_ODL = 0; + + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 2; + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 2; + + DevConfig->Config.Clock[i].DCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ALDY = 0; + + DevConfig->Config.Clock[i].SDCLKout_HS = 0; + DevConfig->Config.Clock[i].SDCLKout_DDLY = 0; + DevConfig->Config.Clock[i].SDCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_HS = 0; + + DevConfig->Config.Clock[i].SDCLK_ADLY = 0; + DevConfig->Config.Clock[i].SDCLKout_ADLY_EN = 0; + + DevConfig->Config.Clock[i].SDCLKout_PD = 0; + DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0; + DevConfig->Config.Clock[i].CLKout_PD = 0; + DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1; + DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1; + DevConfig->Config.Clock[i].DCLKout_HSg_PD = 0; + DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 0; + + DevConfig->Config.Clock[i].DCLKout_FMT = 1; + DevConfig->Config.Clock[i].DCLKout_POL = 0; + DevConfig->Config.Clock[i].SDCLKout_FMT = 1; + DevConfig->Config.Clock[i].SDCLKout_POL = 0; + } + else + { + DevConfig->Config.Clock[i].DCLKout_Div = 0; + DevConfig->Config.Clock[i].CLKout_IDL = 0; + DevConfig->Config.Clock[i].CLKout_ODL = 0; + + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTL = 5; + DevConfig->Config.Clock[i].DCLKout_DDLY_CNTH = 5; + + DevConfig->Config.Clock[i].DCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ADLY_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_ALDY = 0; + + DevConfig->Config.Clock[i].SDCLKout_HS = 0; + DevConfig->Config.Clock[i].SDCLKout_DDLY = 0; + DevConfig->Config.Clock[i].SDCLKout_MUX = 1; + DevConfig->Config.Clock[i].DCLKout_HS = 0; + + DevConfig->Config.Clock[i].SDCLK_ADLY = 0; + DevConfig->Config.Clock[i].SDCLKout_ADLY_EN = 0; + + DevConfig->Config.Clock[i].SDCLKout_PD = 1; + DevConfig->Config.Clock[i].SDCLKout_DIS_MODE = 0; + DevConfig->Config.Clock[i].CLKout_PD = 1; + DevConfig->Config.Clock[i].DCLKout_ADLY_PD = 1; + DevConfig->Config.Clock[i].DCLKout_ADLYg_PD = 1; + DevConfig->Config.Clock[i].DCLKout_HSg_PD = 1; + DevConfig->Config.Clock[i].DCLKout_DDLY_PD = 1; + + DevConfig->Config.Clock[i].DCLKout_FMT = 0; + DevConfig->Config.Clock[i].DCLKout_POL = 0; + DevConfig->Config.Clock[i].SDCLKout_FMT = 0; + DevConfig->Config.Clock[i].SDCLKout_POL = 0; + } + } + return LMK_SUCCESS; +} + +int LMK_WriteReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 Value) +{ + u8 buf[3]; + + buf[0] = 0x0 | ((RegisterAddress >> 8) & 0x1F); + buf[1] = RegisterAddress & 0xFF; + buf[2] = Value; + + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00); + XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, NULL, 3); + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F); + + return LMK_SUCCESS; +} + +int LMK_ReadReg(LMK_Config *DevConfig, u16 RegisterAddress, u8 *Value) +{ + u8 buf[3]; + + buf[0] = 0x80 | ((RegisterAddress >> 8) & 0x1F); + buf[1] = RegisterAddress & 0xFF; + buf[2] = 0; + + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x00); + XSpiPs_PolledTransfer((XSpiPs *)DevConfig->InterfaceInst, buf, buf, 3); + XSpiPs_SetSlaveSelect((XSpiPs *)DevConfig->InterfaceInst, 0x0F); + + *Value = buf[2]; + + return LMK_SUCCESS; +} + +#endif //LMK_PRESET_IW_RFSOC_2T2R_INTERNAL + +#ifdef LMK_PRESET_IW_RFSOC_2T2R_EXTERNAL +#endif //LMK_PRESET_IW_RFSOC_2T2R_EXTERNAL \ No newline at end of file diff --git a/LMK_Preset.h b/LMK_Preset.h new file mode 100644 index 0000000..3acbc00 --- /dev/null +++ b/LMK_Preset.h @@ -0,0 +1,19 @@ +/* + * LMK_Preset.h + * + * Created on: 2025.01.16 + * Author: TiferKing + */ + +#ifndef SRC_LMK_PRESET_H_ +#define SRC_LMK_PRESET_H_ + +#include "LMK_ClockTree.h" + +#define LMK_PRESET_NONE +//#define LMK_PRESET_IW_RFSOC_2T2R_INTERNAL +//#define LMK_PRESET_IW_RFSOC_2T2R_EXTERNAL + +int LMK_ConfigPreset(LMK_Config *DevConfig, LMK_Simple *SimpleConfig); + +#endif /* SRC_LMK_PRESET_H_ */ \ No newline at end of file