Initial commit
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LICENSE
2
LICENSE
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MIT License
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MIT License
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Copyright (c) 2025 IW-RFSOC-2T2R
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Copyright (c) 2025 15inTech(www.15zk.net)
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Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
|
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
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@ -1,2 +1,4 @@
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# IW-RFSOC-2T2R-Board
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# IW-RFSOC-2T2R 板卡文件
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将文件夹iw-rfsoc-2t2r-47dr复制进 Vivado/<version>/data/boards/board_files/ ，如果没有board_files目录就自行创建一个。打开Vivado即可选取“IW-RFSOC-2T2R”板卡。
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21
iw-rfsoc-2t2r-47dr/1.0/LICENSE
Normal file
21
iw-rfsoc-2t2r-47dr/1.0/LICENSE
Normal file
@ -0,0 +1,21 @@
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MIT License
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Copyright (c) 2025 15inTech(www.15zk.net)
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
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||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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||||||
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copies of the Software, and to permit persons to whom the Software is
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||||||
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furnished to do so, subject to the following conditions:
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||||||
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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828
iw-rfsoc-2t2r-47dr/1.0/board.xml
Normal file
828
iw-rfsoc-2t2r-47dr/1.0/board.xml
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<?xml version="1.0" encoding="utf-8"?>
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<board schema_version="2.2" vendor="15zk.net" name="iw-rfsoc-2t2r-47dr" display_name="Interwiser RFSoC 2T2R Development Kit (47DR)" url="https://wiki.15zk.net/zh/boards/IW-RFSOC-2T2R" preset_file="preset.xml" supports_ced="false">
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<images>
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<image name="iw-rfsoc-2t2r-47dr_image.jpg" display_name="IW-RFSOC-2T2R BOARD" sub_type="board" resolution="high">
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<description>IW-RFSOC-2T2R BOARD File Image</description>
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</image>
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</images>
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<compatible_board_revisions>
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<revision id="0">Ver 1.1</revision>
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</compatible_board_revisions>
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<file_version>1.0</file_version>
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<description>Interwiser RFSoC 2T2R Development Kit (47DR)</description>
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<parameters>
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<parameter name="heat_sink_type" value="medium" value_type="string"/>
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<parameter name="heat_sink_temperature" value_type="range" value_min="20.0" value_max="30.0"/>
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</parameters>
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<jumpers></jumpers>
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<components>
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<component name="part0" display_name="XCZU47DR FPGA" type="fpga" part_name="xczu47dr-ffve1156-2-i" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-ultrascale-plus-rfsoc.html">
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<description>XCZU47DR FPGA</description>
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<interfaces>
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<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset">
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<description>Zynq ARM processors.</description>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
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</preferred_ips>
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</interface>
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<interface mode="slave" name="pl_ref_clk0" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="lmk04828" preset_proc="pl_ref_clk0_preset">
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<description>PL reference clock from LMK04828. </description>
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<parameters>
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<parameter name="frequency" value="491520000"/>
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</parameters>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
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</preferred_ips>
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<port_maps>
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<port_map logical_port="CLK_P" physical_port="pl_ref_clk0_p" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="pl_ref_clk0_p"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="CLK_N" physical_port="pl_ref_clk0_n" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="pl_ref_clk0_n"/>
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</pin_maps>
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</port_map>
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</port_maps>
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</interface>
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<interface mode="slave" name="pl_sysref" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="lmk04828" preset_proc="pl_sysref_preset">
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<description>PL SYSREF from LMK04828. </description>
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<parameters>
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<parameter name="frequency" value="7680000"/>
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</parameters>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="util_ds_buf" order="0"/>
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</preferred_ips>
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<port_maps>
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<port_map logical_port="CLK_P" physical_port="pl_sysref_p" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="pl_sysref_p"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="CLK_N" physical_port="pl_sysref_n" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="pl_sysref_n"/>
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</pin_maps>
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</port_map>
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</port_maps>
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</interface>
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<interface mode="slave" name="ddr4_clk0" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="ddr4_osc" preset_proc="ddr4_clk0_preset">
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<description>DDR4 reference clock. </description>
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<parameters>
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<parameter name="frequency" value="300000000"/>
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</parameters>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
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<preferred_ip vendor="xilinx.com" library="ip" name="util_ds_buf" order="1"/>
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</preferred_ips>
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<port_maps>
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<port_map logical_port="CLK_P" physical_port="ddr4_clk0_p" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="ddr4_clk0_p"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="CLK_N" physical_port="ddr4_clk0_n" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="ddr4_clk0_n"/>
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</pin_maps>
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</port_map>
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</port_maps>
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</interface>
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<interface mode="master" name="ddr4_sdram" type="xilinx.com:interface:ddr4_rtl:1.0" of_component="ddr4_sdram" preset_proc="ddr4_sdram_preset">
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<description>DDR4 on board interface, it can use DDR4 controller IP for connection. </description>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="ddr4" order="0"/>
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</preferred_ips>
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<port_maps>
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<port_map logical_port="ACT_N" physical_port="c0_ddr4_act_n" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_act_n"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="ADR" physical_port="c0_ddr4_adr" dir="out" left="16" right="0">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_adr0"/>
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<pin_map port_index="1" component_pin="c0_ddr4_adr1"/>
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<pin_map port_index="2" component_pin="c0_ddr4_adr2"/>
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<pin_map port_index="3" component_pin="c0_ddr4_adr3"/>
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<pin_map port_index="4" component_pin="c0_ddr4_adr4"/>
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<pin_map port_index="5" component_pin="c0_ddr4_adr5"/>
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<pin_map port_index="6" component_pin="c0_ddr4_adr6"/>
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<pin_map port_index="7" component_pin="c0_ddr4_adr7"/>
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<pin_map port_index="8" component_pin="c0_ddr4_adr8"/>
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<pin_map port_index="9" component_pin="c0_ddr4_adr9"/>
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<pin_map port_index="10" component_pin="c0_ddr4_adr10"/>
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<pin_map port_index="11" component_pin="c0_ddr4_adr11"/>
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<pin_map port_index="12" component_pin="c0_ddr4_adr12"/>
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<pin_map port_index="13" component_pin="c0_ddr4_adr13"/>
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<pin_map port_index="14" component_pin="c0_ddr4_adr14"/>
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<pin_map port_index="15" component_pin="c0_ddr4_adr15"/>
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<pin_map port_index="16" component_pin="c0_ddr4_adr16"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="BA" physical_port="c0_ddr4_ba" dir="out" left="1" right="0">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_ba0"/>
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<pin_map port_index="1" component_pin="c0_ddr4_ba1"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="BG" physical_port="c0_ddr4_bg" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_bg"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="CK_C" physical_port="c0_ddr4_ck_c" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_ck_c"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="CK_T" physical_port="c0_ddr4_ck_t" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_ck_t"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="CKE" physical_port="c0_ddr4_cke" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_cke"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="CS_N" physical_port="c0_ddr4_cs_n" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_cs_n"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="DM_N" physical_port="c0_ddr4_dm_dbi_n" dir="inout" left="3" right="0">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_dm_dbi_n0"/>
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<pin_map port_index="1" component_pin="c0_ddr4_dm_dbi_n1"/>
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<pin_map port_index="2" component_pin="c0_ddr4_dm_dbi_n2"/>
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<pin_map port_index="3" component_pin="c0_ddr4_dm_dbi_n3"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="DQ" physical_port="c0_ddr4_dq" dir="inout" left="31" right="0">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_dq0"/>
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<pin_map port_index="1" component_pin="c0_ddr4_dq1"/>
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<pin_map port_index="2" component_pin="c0_ddr4_dq2"/>
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<pin_map port_index="3" component_pin="c0_ddr4_dq3"/>
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<pin_map port_index="4" component_pin="c0_ddr4_dq4"/>
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<pin_map port_index="5" component_pin="c0_ddr4_dq5"/>
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<pin_map port_index="6" component_pin="c0_ddr4_dq6"/>
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<pin_map port_index="7" component_pin="c0_ddr4_dq7"/>
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<pin_map port_index="8" component_pin="c0_ddr4_dq8"/>
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<pin_map port_index="9" component_pin="c0_ddr4_dq9"/>
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<pin_map port_index="10" component_pin="c0_ddr4_dq10"/>
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<pin_map port_index="11" component_pin="c0_ddr4_dq11"/>
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<pin_map port_index="12" component_pin="c0_ddr4_dq12"/>
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<pin_map port_index="13" component_pin="c0_ddr4_dq13"/>
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<pin_map port_index="14" component_pin="c0_ddr4_dq14"/>
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<pin_map port_index="15" component_pin="c0_ddr4_dq15"/>
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<pin_map port_index="16" component_pin="c0_ddr4_dq16"/>
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<pin_map port_index="17" component_pin="c0_ddr4_dq17"/>
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<pin_map port_index="18" component_pin="c0_ddr4_dq18"/>
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<pin_map port_index="19" component_pin="c0_ddr4_dq19"/>
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<pin_map port_index="20" component_pin="c0_ddr4_dq20"/>
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<pin_map port_index="21" component_pin="c0_ddr4_dq21"/>
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<pin_map port_index="22" component_pin="c0_ddr4_dq22"/>
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<pin_map port_index="23" component_pin="c0_ddr4_dq23"/>
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<pin_map port_index="24" component_pin="c0_ddr4_dq24"/>
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<pin_map port_index="25" component_pin="c0_ddr4_dq25"/>
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<pin_map port_index="26" component_pin="c0_ddr4_dq26"/>
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<pin_map port_index="27" component_pin="c0_ddr4_dq27"/>
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<pin_map port_index="28" component_pin="c0_ddr4_dq28"/>
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<pin_map port_index="29" component_pin="c0_ddr4_dq29"/>
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<pin_map port_index="30" component_pin="c0_ddr4_dq30"/>
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<pin_map port_index="31" component_pin="c0_ddr4_dq31"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="DQS_C" physical_port="c0_ddr4_dqs_c" dir="inout" left="3" right="0">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_dqs0_c"/>
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<pin_map port_index="1" component_pin="c0_ddr4_dqs1_c"/>
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<pin_map port_index="2" component_pin="c0_ddr4_dqs2_c"/>
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<pin_map port_index="3" component_pin="c0_ddr4_dqs3_c"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="DQS_T" physical_port="c0_ddr4_dqs_t" dir="out" left="3" right="0">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_dqs0_t"/>
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<pin_map port_index="1" component_pin="c0_ddr4_dqs1_t"/>
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<pin_map port_index="2" component_pin="c0_ddr4_dqs2_t"/>
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<pin_map port_index="3" component_pin="c0_ddr4_dqs3_t"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="ODT" physical_port="c0_ddr4_odt" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_odt"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="RESET_N" physical_port="c0_ddr4_reset_n" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="c0_ddr4_reset_n"/>
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</pin_maps>
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</port_map>
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</port_maps>
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</interface>
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||||||
|
<interface mode="slave" name="sfp_mgt_clk0" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sfp">
|
||||||
|
<description>SFP MGT reference clock. </description>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="frequency" value="156250000"/>
|
||||||
|
</parameters>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="l_ethernet" order="1"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="2"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="cmac_usplus" order="3"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="CLK_P" physical_port="sfp_mgt_clk0_p" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="sfp_mgt_clk0_p"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="CLK_N" physical_port="sfp_mgt_clk0_n" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="sfp_mgt_clk0_n"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="sfp_1x" type="xilinx.com:interface:gt_rtl:1.0" of_component="sfp">
|
||||||
|
<description>1-lane GT interface over SFP</description>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="GTX_N" physical_port="sfp_txn0" dir="out">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="sfp_txn0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GTX_P" physical_port="sfp_txp0" dir="out">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="sfp_txp0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_N" physical_port="sfp_rxn0" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="sfp_rxn0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_P" physical_port="sfp_rxp0" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="sfp_rxp0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="gt_loc" value="" />
|
||||||
|
</parameters>
|
||||||
|
</interface>
|
||||||
|
<interface mode="slave" name="qsfp_mgt_clk0" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="qsfp">
|
||||||
|
<description>QSFP MGT reference clock. </description>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="frequency" value="156250000"/>
|
||||||
|
</parameters>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="l_ethernet" order="1"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="2"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="cmac_usplus" order="3"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="CLK_P" physical_port="qsfp_mgt_clk0_p" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_mgt_clk0_p"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="CLK_N" physical_port="qsfp_mgt_clk0_n" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_mgt_clk0_n"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="qsfp_1x" type="xilinx.com:interface:gt_rtl:1.0" of_component="qsfp">
|
||||||
|
<description>1-lane GT interface over QSFP</description>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="1"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="GTX_N" physical_port="qsfp_txn1" dir="out">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txn0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GTX_P" physical_port="qsfp_txp1" dir="out">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txp0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_N" physical_port="qsfp_rxn1" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxn0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_P" physical_port="qsfp_rxp1" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxp0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="gt_loc" value="" />
|
||||||
|
</parameters>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="qsfp_2x" type="xilinx.com:interface:gt_rtl:1.0" of_component="qsfp">
|
||||||
|
<description>2-lane GT interface over QSFP</description>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="l_ethernet" order="1"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="2"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="GTX_N" physical_port="qsfp_txn2" dir="out" left="1" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txn0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_txn1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GTX_P" physical_port="qsfp_txp2" dir="out" left="1" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txp0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_txp1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_N" physical_port="qsfp_rxn2" dir="in" left="1" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxn0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_rxn1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_P" physical_port="qsfp_rxp2" dir="in" left="1" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxp0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_rxp1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="gt_loc" value="" />
|
||||||
|
</parameters>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="qsfp_3x" type="xilinx.com:interface:gt_rtl:1.0" of_component="qsfp">
|
||||||
|
<description>3-lane GT interface over QSFP</description>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="1"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="GTX_N" physical_port="qsfp_txn3" dir="out" left="2" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txn0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_txn1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_txn2"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GTX_P" physical_port="qsfp_txp3" dir="out" left="2" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txp0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_txp1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_txp2"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_N" physical_port="qsfp_rxn3" dir="in" left="2" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxn0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_rxn1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_rxn2"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_P" physical_port="qsfp_rxp3" dir="in" left="2" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxp0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_rxp1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_rxp2"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="gt_loc" value="" />
|
||||||
|
</parameters>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="qsfp_4x" type="xilinx.com:interface:gt_rtl:1.0" of_component="qsfp">
|
||||||
|
<description>4-lane GT interface over QSFP</description>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="l_ethernet" order="1"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="2"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="cmac_usplus" order="3"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="GTX_N" physical_port="qsfp_txn4" dir="out" left="3" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txn0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_txn1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_txn2"/>
|
||||||
|
<pin_map port_index="3" component_pin="qsfp_txn3"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GTX_P" physical_port="qsfp_txp4" dir="out" left="3" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_txp0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_txp1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_txp2"/>
|
||||||
|
<pin_map port_index="3" component_pin="qsfp_txp3"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_N" physical_port="qsfp_rxn4" dir="in" left="3" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxn0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_rxn1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_rxn2"/>
|
||||||
|
<pin_map port_index="3" component_pin="qsfp_rxn3"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="GRX_P" physical_port="qsfp_rxp4" dir="in" left="3" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="qsfp_rxp0"/>
|
||||||
|
<pin_map port_index="1" component_pin="qsfp_rxp1"/>
|
||||||
|
<pin_map port_index="2" component_pin="qsfp_rxp2"/>
|
||||||
|
<pin_map port_index="3" component_pin="qsfp_rxp3"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="gt_loc" value="" />
|
||||||
|
</parameters>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="iic_eeprom" type="xilinx.com:interface:iic_rtl:1.0" of_component="iic_eeprom">
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="SDA_I" physical_port="iic_eeprom_sda_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="IIC_SDA_EEPROM"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SDA_O" physical_port="iic_eeprom_sda_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="IIC_SDA_EEPROM"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SDA_T" physical_port="iic_eeprom_sda_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="IIC_SDA_EEPROM"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCL_I" physical_port="iic_eeprom_scl_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="IIC_SCL_EEPROM"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCL_O" physical_port="iic_eeprom_scl_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="IIC_SCL_EEPROM"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCL_T" physical_port="iic_eeprom_scl_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="IIC_SCL_EEPROM"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="slave" name="resetn" type="xilinx.com:signal:reset_rtl:1.0" of_component="pmod_ext">
|
||||||
|
<description>Reset button from PMOD Extender. </description>
|
||||||
|
<parameters>
|
||||||
|
<parameter name="rst_polarity" value="0"/>
|
||||||
|
</parameters>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="RST" physical_port="reset" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SW_RESET"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="led_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_8bits" preset_proc="led_8bits_preset">
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="TRI_O" physical_port="leds_8bits_tri_o" dir="out" left="7" right="0">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="GPIO_LED_0"/>
|
||||||
|
<pin_map port_index="1" component_pin="GPIO_LED_1"/>
|
||||||
|
<pin_map port_index="2" component_pin="GPIO_LED_2"/>
|
||||||
|
<pin_map port_index="3" component_pin="GPIO_LED_3"/>
|
||||||
|
<pin_map port_index="4" component_pin="GPIO_LED_4"/>
|
||||||
|
<pin_map port_index="5" component_pin="GPIO_LED_5"/>
|
||||||
|
<pin_map port_index="6" component_pin="GPIO_LED_6"/>
|
||||||
|
<pin_map port_index="7" component_pin="GPIO_LED_7"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="rs232_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="rs232" preset_proc="rs232_uart_preset">
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="axi_uart16550" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="TxD" physical_port="rs232_uart_txd" dir="out">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="rs232_tx"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="RxD" physical_port="rs232_uart_rxd" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="rs232_rx"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="gps_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="gps" preset_proc="gps_uart_preset">
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="axi_uart16550" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="TxD" physical_port="gps_uart_txd" dir="out">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="gps_tx"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="RxD" physical_port="gps_uart_rxd" dir="in">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="gps_rx"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="j30j_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="j30j">
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="IO0_I" physical_port="spi_io0_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_D0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO0_O" physical_port="spi_io0_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_D0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO0_T" physical_port="spi_io0_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_D0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO1_I" physical_port="spi_io1_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_D1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO1_O" physical_port="spi_io1_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_D1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO1_T" physical_port="spi_io1_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_D1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SS_I" physical_port="spi_ss_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_FCS"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SS_O" physical_port="spi_ss_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_FCS"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SS_T" physical_port="spi_ss_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_FCS"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCK_I" physical_port="spi_sck_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_CCLK"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCK_O" physical_port="spi_sck_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_CCLK"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCK_T" physical_port="spi_sck_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="SPI_CCLK"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
<interface mode="master" name="lmk_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="lmk04828">
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||||
|
</preferred_ips>
|
||||||
|
<port_maps>
|
||||||
|
<port_map logical_port="IO0_I" physical_port="lmk_spi_io0_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_D0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO0_O" physical_port="lmk_spi_io0_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_D0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO0_T" physical_port="lmk_spi_io0_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_D0"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO1_I" physical_port="lmk_spi_io1_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_D1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO1_O" physical_port="lmk_spi_io1_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_D1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="IO1_T" physical_port="lmk_spi_io1_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_D1"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SS_I" physical_port="lmk_spi_ss_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_FCS"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SS_O" physical_port="lmk_spi_ss_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_FCS"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SS_T" physical_port="lmk_spi_ss_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_FCS"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCK_I" physical_port="lmk_spi_sck_i" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_CCLK"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCK_O" physical_port="lmk_spi_sck_o" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_CCLK"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
<port_map logical_port="SCK_T" physical_port="lmk_spi_sck_t" dir="inout">
|
||||||
|
<pin_maps>
|
||||||
|
<pin_map port_index="0" component_pin="LMK_SPI_CCLK"/>
|
||||||
|
</pin_maps>
|
||||||
|
</port_map>
|
||||||
|
</port_maps>
|
||||||
|
</interface>
|
||||||
|
</interfaces>
|
||||||
|
</component>
|
||||||
|
<component name="ps8_fixedio" display_name="PS8 fixed IO" type="chip" sub_type="fixed_io" major_group="">
|
||||||
|
<description>Zynq ARM fixed IO.</description>
|
||||||
|
</component>
|
||||||
|
<component name="lmk04828" display_name="LMK04828 Clock Tree" type="chip" sub_type="chip" major_group="Clock Sources" part_name="LMK04828" vendor="Texas Instrument" spec_url="">
|
||||||
|
<description>LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs</description>
|
||||||
|
</component>
|
||||||
|
<component name="ddr4_osc" display_name="DDR4 reference clock" type="chip" sub_type="system_clock" major_group="Clock Sources">
|
||||||
|
<description>DDR4 reference clock.</description>
|
||||||
|
</component>
|
||||||
|
<component name="ddr4_sdram" display_name="DDR4 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
|
||||||
|
<description>2GB DDR4 memory Components</description>
|
||||||
|
</component>
|
||||||
|
<component name="sfp" display_name="SFP Connector" type="chip" sub_type="sfp" major_group="Ethernet Configurations">
|
||||||
|
<description>SFP Connector</description>
|
||||||
|
</component>
|
||||||
|
<component name="qsfp" display_name="QSFP Connector" type="chip" sub_type="sfp" major_group="Ethernet Configurations">
|
||||||
|
<description>QSFP Connector</description>
|
||||||
|
<component_modes>
|
||||||
|
<component_mode name="qsfp_1x" display_name="qsfp_1x">
|
||||||
|
<interfaces>
|
||||||
|
<interface name="qsfp_1x"/>
|
||||||
|
<interface name="qsfp_mgt_clk0" optional="true"/>
|
||||||
|
</interfaces>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="1"/>
|
||||||
|
</preferred_ips>
|
||||||
|
</component_mode>
|
||||||
|
<component_mode name="qsfp_2x" display_name="qsfp_2x">
|
||||||
|
<interfaces>
|
||||||
|
<interface name="qsfp_2x"/>
|
||||||
|
<interface name="qsfp_mgt_clk0" optional="true"/>
|
||||||
|
</interfaces>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="l_ethernet" order="1"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="2"/>
|
||||||
|
</preferred_ips>
|
||||||
|
</component_mode>
|
||||||
|
<component_mode name="qsfp_3x" display_name="qsfp_3x">
|
||||||
|
<interfaces>
|
||||||
|
<interface name="qsfp_3x"/>
|
||||||
|
<interface name="qsfp_mgt_clk0" optional="true"/>
|
||||||
|
</interfaces>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="1"/>
|
||||||
|
</preferred_ips>
|
||||||
|
</component_mode>
|
||||||
|
<component_mode name="qsfp_4x" display_name="qsfp_4x">
|
||||||
|
<interfaces>
|
||||||
|
<interface name="qsfp_4x"/>
|
||||||
|
<interface name="qsfp_mgt_clk0" optional="true"/>
|
||||||
|
</interfaces>
|
||||||
|
<preferred_ips>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="xxv_ethernet" order="0"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="l_ethernet" order="1"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="interlaken" order="2"/>
|
||||||
|
<preferred_ip vendor="xilinx.com" library="ip" name="cmac_usplus" order="3"/>
|
||||||
|
</preferred_ips>
|
||||||
|
</component_mode>
|
||||||
|
</component_modes>
|
||||||
|
</component>
|
||||||
|
<component name="iic_eeprom" display_name="EEPROM" type="chip" sub_type="chip" major_group="Miscellaneous" part_name="M24C08" vendor="STMicroelectronics">
|
||||||
|
<description>8-Kbit serial IIC bus EEPROM.</description>
|
||||||
|
</component>
|
||||||
|
<component name="pmod_ext" display_name="PMOD Extender" type="chip" sub_type="chip" major_group="Reset" part_name="PMOD_EXT" vendor="15inTech" spec_url="https://wiki.15zk.net/zh/module/YWM-PMODEXT">
|
||||||
|
<description>PMOD extender.</description>
|
||||||
|
</component>
|
||||||
|
<component name="led_8bits" display_name="User LEDs" type="chip" sub_type="led" major_group="LED" part_name="LED" vendor="Unknown">
|
||||||
|
<description>8 LEDs on board.</description>
|
||||||
|
</component>
|
||||||
|
<component name="rs232" display_name="RS232" type="chip" sub_type="uart" major_group="Miscellaneous">
|
||||||
|
<description>PL RS232.</description>
|
||||||
|
</component>
|
||||||
|
<component name="gps" display_name="GPS" type="chip" sub_type="uart" major_group="Miscellaneous">
|
||||||
|
<description>GPS Module on board.</description>
|
||||||
|
</component>
|
||||||
|
<component name="j30j" display_name="J30J Connector" type="chip" sub_type="chip" major_group="Miscellaneous">
|
||||||
|
<description>J30J Connector</description>
|
||||||
|
</component>
|
||||||
|
</components>
|
||||||
|
<jtag_chains>
|
||||||
|
<jtag_chain name="chain1">
|
||||||
|
<position name="0" component="part0"/>
|
||||||
|
</jtag_chain>
|
||||||
|
</jtag_chains>
|
||||||
|
<connections>
|
||||||
|
<connection name="part0_lmk04828" component1="part0" component2="lmk04828">
|
||||||
|
<connection_map name="part0_lmk04828_1" typical_delay="5" c1_st_index="0" c1_end_index="7" c2_st_index="0" c2_end_index="7"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_ddr4_osc" component1="part0" component2="ddr4_osc">
|
||||||
|
<connection_map name="part0_ddr4_osc_1" typical_delay="5" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_ddr4_sdram" component1="part0" component2="ddr4_sdram">
|
||||||
|
<connection_map name="part0_ddr4_sdram_1" typical_delay="5" c1_st_index="30" c1_end_index="101" c2_st_index="0" c2_end_index="71"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_sfp" component1="part0" component2="sfp">
|
||||||
|
<connection_map name="part0_sfp_1" typical_delay="5" c1_st_index="120" c1_end_index="125" c2_st_index="0" c2_end_index="5"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_qsfp" component1="part0" component2="qsfp">
|
||||||
|
<connection_map name="part0_qsfp_1" typical_delay="5" c1_st_index="120" c1_end_index="137" c2_st_index="0" c2_end_index="17"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_iic_eeprom" component1="part0" component2="iic_eeprom">
|
||||||
|
<connection_map name="part0_iic_eeprom_1" typical_delay="5" c1_st_index="140" c1_end_index="141" c2_st_index="0" c2_end_index="1"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_pmod_ext" component1="part0" component2="pmod_ext">
|
||||||
|
<connection_map name="part0_pmod_ext_1" typical_delay="5" c1_st_index="150" c1_end_index="150" c2_st_index="0" c2_end_index="0"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_led_8bits" component1="part0" component2="led_8bits">
|
||||||
|
<connection_map name="part0_led_8bits_1" typical_delay="5" c1_st_index="150" c1_end_index="157" c2_st_index="0" c2_end_index="7"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_rs232" component1="part0" component2="rs232">
|
||||||
|
<connection_map name="part0_rs232_1" typical_delay="5" c1_st_index="160" c1_end_index="161" c2_st_index="0" c2_end_index="1"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_gps" component1="part0" component2="gps">
|
||||||
|
<connection_map name="part0_gps_1" c1_st_index="170" c1_end_index="171" c2_st_index="0" c2_end_index="1"/>
|
||||||
|
</connection>
|
||||||
|
<connection name="part0_j30j" component1="part0" component2="j30j">
|
||||||
|
<connection_map name="part0_j30j_1" c1_st_index="180" c1_end_index="183" c2_st_index="0" c2_end_index="3"/>
|
||||||
|
</connection>
|
||||||
|
</connections>
|
||||||
|
<ip_associated_rules>
|
||||||
|
<ip_associated_rule name="default"></ip_associated_rule>
|
||||||
|
</ip_associated_rules>
|
||||||
|
</board>
|
||||||
BIN
iw-rfsoc-2t2r-47dr/1.0/iw-rfsoc-2t2r-47dr_image.jpg
Normal file
BIN
iw-rfsoc-2t2r-47dr/1.0/iw-rfsoc-2t2r-47dr_image.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 129 KiB |
141
iw-rfsoc-2t2r-47dr/1.0/part0_pins.xml
Normal file
141
iw-rfsoc-2t2r-47dr/1.0/part0_pins.xml
Normal file
@ -0,0 +1,141 @@
|
|||||||
|
<?xml version="1.0" encoding="utf-8"?>
|
||||||
|
|
||||||
|
<part_info part_name="xczu47dr-ffve1156-2-i">
|
||||||
|
<pins>
|
||||||
|
<pin index="0" name="pl_ref_clk0_p" iostandard="LVDS" loc="AP11" dqs_bias="TRUE"/>
|
||||||
|
<pin index="1" name="pl_ref_clk0_n" iostandard="LVDS" loc="AP10" dqs_bias="TRUE"/>
|
||||||
|
<pin index="2" name="pl_sysref_p" iostandard="LVDS" loc="AM10" dqs_bias="TRUE"/>
|
||||||
|
<pin index="3" name="pl_sysref_n" iostandard="LVDS" loc="AN10" dqs_bias="TRUE"/>
|
||||||
|
<pin index="4" name="LMK_SPI_D0" iostandard="LVCMOS33" loc="B11" drive="8" slew="FAST"/>
|
||||||
|
<pin index="5" name="LMK_SPI_D1" iostandard="LVCMOS33" loc="E12" drive="8" slew="FAST"/>
|
||||||
|
<pin index="6" name="LMK_SPI_FCS" iostandard="LVCMOS33" loc="A10" drive="8" slew="FAST"/>
|
||||||
|
<pin index="7" name="LMK_SPI_CCLK" iostandard="LVCMOS33" loc="G11" drive="8" slew="FAST"/>
|
||||||
|
|
||||||
|
<pin index="8" name="ddr4_clk0_p" iostandard="LVDS" loc="AL9" dqs_bias="TRUE"/>
|
||||||
|
<pin index="9" name="ddr4_clk0_n" iostandard="LVDS" loc="AM9" dqs_bias="TRUE"/>
|
||||||
|
|
||||||
|
<pin index="10" name="SW_RESET" iostandard="LVCMOS33" loc="F9" drive="8" slew="FAST"/>
|
||||||
|
|
||||||
|
<pin index="30" name ="c0_ddr4_act_n" loc="AN8" />
|
||||||
|
<pin index="31" name ="c0_ddr4_adr0" loc="AG12" />
|
||||||
|
<pin index="32" name ="c0_ddr4_adr1" loc="AJ11" />
|
||||||
|
<pin index="33" name ="c0_ddr4_adr2" loc="AH10" />
|
||||||
|
<pin index="34" name ="c0_ddr4_adr3" loc="AH9" />
|
||||||
|
<pin index="35" name ="c0_ddr4_adr4" loc="AG10" />
|
||||||
|
<pin index="36" name ="c0_ddr4_adr5" loc="AG9" />
|
||||||
|
<pin index="37" name ="c0_ddr4_adr6" loc="AM11" />
|
||||||
|
<pin index="38" name ="c0_ddr4_adr7" loc="AG11" />
|
||||||
|
<pin index="39" name ="c0_ddr4_adr8" loc="AE11" />
|
||||||
|
<pin index="40" name ="c0_ddr4_adr9" loc="AF10" />
|
||||||
|
<pin index="41" name ="c0_ddr4_adr10" loc="AM12" />
|
||||||
|
<pin index="42" name ="c0_ddr4_adr11" loc="AF12" />
|
||||||
|
<pin index="43" name ="c0_ddr4_adr12" loc="AL12" />
|
||||||
|
<pin index="44" name ="c0_ddr4_adr13" loc="AF11" />
|
||||||
|
<pin index="45" name ="c0_ddr4_adr14" loc="AN12" />
|
||||||
|
<pin index="46" name ="c0_ddr4_adr15" loc="AL11" />
|
||||||
|
<pin index="47" name ="c0_ddr4_adr16" loc="AL13" />
|
||||||
|
<pin index="48" name ="c0_ddr4_ba0" loc="AK9" />
|
||||||
|
<pin index="49" name ="c0_ddr4_ba1" loc="AK10" />
|
||||||
|
<pin index="50" name ="c0_ddr4_bg" loc="AP12" />
|
||||||
|
<pin index="51" name ="c0_ddr4_ck_c" loc="AJ9" />
|
||||||
|
<pin index="52" name ="c0_ddr4_ck_t" loc="AJ10" />
|
||||||
|
<pin index="53" name ="c0_ddr4_cke" loc="AN13" />
|
||||||
|
<pin index="54" name ="c0_ddr4_cs_n" loc="AP13" />
|
||||||
|
<pin index="55" name ="c0_ddr4_dm_dbi_n0" loc="AC13" />
|
||||||
|
<pin index="56" name ="c0_ddr4_dm_dbi_n1" loc="AG15" />
|
||||||
|
<pin index="57" name ="c0_ddr4_dm_dbi_n2" loc="AH13" />
|
||||||
|
<pin index="58" name ="c0_ddr4_dm_dbi_n3" loc="AM14" />
|
||||||
|
<pin index="59" name ="c0_ddr4_dq0" loc="AE14" />
|
||||||
|
<pin index="60" name ="c0_ddr4_dq1" loc="AD16" />
|
||||||
|
<pin index="61" name ="c0_ddr4_dq2" loc="AE15" />
|
||||||
|
<pin index="62" name ="c0_ddr4_dq3" loc="AC17" />
|
||||||
|
<pin index="63" name ="c0_ddr4_dq4" loc="AD15" />
|
||||||
|
<pin index="64" name ="c0_ddr4_dq5" loc="AE18" />
|
||||||
|
<pin index="65" name ="c0_ddr4_dq6" loc="AE13" />
|
||||||
|
<pin index="66" name ="c0_ddr4_dq7" loc="AD18" />
|
||||||
|
<pin index="67" name ="c0_ddr4_dq8" loc="AF13" />
|
||||||
|
<pin index="68" name ="c0_ddr4_dq9" loc="AG17" />
|
||||||
|
<pin index="69" name ="c0_ddr4_dq10" loc="AE16" />
|
||||||
|
<pin index="70" name ="c0_ddr4_dq11" loc="AH17" />
|
||||||
|
<pin index="71" name ="c0_ddr4_dq12" loc="AF14" />
|
||||||
|
<pin index="72" name ="c0_ddr4_dq13" loc="AF17" />
|
||||||
|
<pin index="73" name ="c0_ddr4_dq14" loc="AF16" />
|
||||||
|
<pin index="74" name ="c0_ddr4_dq15" loc="AF18" />
|
||||||
|
<pin index="75" name ="c0_ddr4_dq16" loc="AK15" />
|
||||||
|
<pin index="76" name ="c0_ddr4_dq17" loc="AK18" />
|
||||||
|
<pin index="77" name ="c0_ddr4_dq18" loc="AK16" />
|
||||||
|
<pin index="78" name ="c0_ddr4_dq19" loc="AJ15" />
|
||||||
|
<pin index="79" name ="c0_ddr4_dq20" loc="AK14" />
|
||||||
|
<pin index="80" name ="c0_ddr4_dq21" loc="AL18" />
|
||||||
|
<pin index="81" name ="c0_ddr4_dq22" loc="AJ16" />
|
||||||
|
<pin index="82" name ="c0_ddr4_dq23" loc="AJ17" />
|
||||||
|
<pin index="83" name ="c0_ddr4_dq24" loc="AN17" />
|
||||||
|
<pin index="84" name ="c0_ddr4_dq25" loc="AN18" />
|
||||||
|
<pin index="85" name ="c0_ddr4_dq26" loc="AP16" />
|
||||||
|
<pin index="86" name ="c0_ddr4_dq27" loc="AP17" />
|
||||||
|
<pin index="87" name ="c0_ddr4_dq28" loc="AP15" />
|
||||||
|
<pin index="88" name ="c0_ddr4_dq29" loc="AM17" />
|
||||||
|
<pin index="89" name ="c0_ddr4_dq30" loc="AM15" />
|
||||||
|
<pin index="90" name ="c0_ddr4_dq31" loc="AN15" />
|
||||||
|
<pin index="91" name ="c0_ddr4_dqs0_c" loc="AC15" />
|
||||||
|
<pin index="92" name ="c0_ddr4_dqs0_t" loc="AC16" />
|
||||||
|
<pin index="93" name ="c0_ddr4_dqs1_c" loc="AH14" />
|
||||||
|
<pin index="94" name ="c0_ddr4_dqs1_t" loc="AG14" />
|
||||||
|
<pin index="95" name ="c0_ddr4_dqs2_c" loc="AJ18" />
|
||||||
|
<pin index="96" name ="c0_ddr4_dqs2_t" loc="AH18" />
|
||||||
|
<pin index="97" name ="c0_ddr4_dqs3_c" loc="AM16" />
|
||||||
|
<pin index="98" name ="c0_ddr4_dqs3_t" loc="AL17" />
|
||||||
|
<pin index="99" name ="c0_ddr4_odt" loc="AK13" />
|
||||||
|
<pin index="100" name ="c0_ddr4_reset_n" iostandard="LVCMOS12" loc="AN7" drive="8"/>
|
||||||
|
<pin index="101" name ="c0_ddr4_parity" loc="D19" />
|
||||||
|
|
||||||
|
<pin index="110" name="sfp_mgt_clk0_p" loc="H28"/>
|
||||||
|
<pin index="111" name="sfp_mgt_clk0_n" loc="H29"/>
|
||||||
|
<pin index="112" name="sfp_txn0" loc="E31"/>
|
||||||
|
<pin index="113" name="sfp_txp0" loc="E30"/>
|
||||||
|
<pin index="114" name="sfp_rxn0" loc="F34"/>
|
||||||
|
<pin index="115" name="sfp_rxp0" loc="F33"/>
|
||||||
|
|
||||||
|
<pin index="120" name="qsfp_mgt_clk0_p" loc="M28"/>
|
||||||
|
<pin index="121" name="qsfp_mgt_clk0_n" loc="M29"/>
|
||||||
|
<pin index="122" name="qsfp_txn0" loc="N31"/>
|
||||||
|
<pin index="123" name="qsfp_txp0" loc="N30"/>
|
||||||
|
<pin index="124" name="qsfp_rxn0" loc="P34"/>
|
||||||
|
<pin index="125" name="qsfp_rxp0" loc="P33"/>
|
||||||
|
<pin index="126" name="qsfp_txn1" loc="L31"/>
|
||||||
|
<pin index="127" name="qsfp_txp1" loc="L30"/>
|
||||||
|
<pin index="128" name="qsfp_rxn1" loc="M34"/>
|
||||||
|
<pin index="129" name="qsfp_rxp1" loc="M33"/>
|
||||||
|
<pin index="130" name="qsfp_txn2" loc="J31"/>
|
||||||
|
<pin index="131" name="qsfp_txp2" loc="J30"/>
|
||||||
|
<pin index="132" name="qsfp_rxn2" loc="K34"/>
|
||||||
|
<pin index="133" name="qsfp_rxp2" loc="K33"/>
|
||||||
|
<pin index="134" name="qsfp_txn3" loc="G31"/>
|
||||||
|
<pin index="135" name="qsfp_txp3" loc="G30"/>
|
||||||
|
<pin index="136" name="qsfp_rxn3" loc="H34"/>
|
||||||
|
<pin index="137" name="qsfp_rxp3" loc="H33"/>
|
||||||
|
|
||||||
|
<pin index="140" name="IIC_SDA_EEPROM" iostandard="LVCMOS33" loc="C11" drive="8" slew="FAST"/>
|
||||||
|
<pin index="141" name="IIC_SCL_EEPROM" iostandard="LVCMOS33" loc="B10" drive="8" slew="FAST"/>
|
||||||
|
|
||||||
|
<pin index="150" name="GPIO_LED_0" iostandard="LVCMOS12" loc="AN9" drive="8" slew="FAST"/>
|
||||||
|
<pin index="151" name="GPIO_LED_1" iostandard="LVCMOS12" loc="AM8" drive="8" slew="FAST"/>
|
||||||
|
<pin index="152" name="GPIO_LED_2" iostandard="LVCMOS12" loc="AM7" drive="8" slew="FAST"/>
|
||||||
|
<pin index="153" name="GPIO_LED_3" iostandard="LVCMOS12" loc="AP7" drive="8" slew="FAST"/>
|
||||||
|
<pin index="154" name="GPIO_LED_4" iostandard="LVCMOS12" loc="AM6" drive="8" slew="FAST"/>
|
||||||
|
<pin index="155" name="GPIO_LED_5" iostandard="LVCMOS12" loc="AP6" drive="8" slew="FAST"/>
|
||||||
|
<pin index="156" name="GPIO_LED_6" iostandard="LVCMOS12" loc="AN5" drive="8" slew="FAST"/>
|
||||||
|
<pin index="157" name="GPIO_LED_7" iostandard="LVCMOS12" loc="AP5" drive="8" slew="FAST"/>
|
||||||
|
|
||||||
|
<pin index="160" name="rs232_tx" iostandard="LVCMOS33" loc="C10" drive="8" slew="FAST"/>
|
||||||
|
<pin index="161" name="rs232_rx" iostandard="LVCMOS33" loc="C9" drive="8" slew="FAST"/>
|
||||||
|
|
||||||
|
<pin index="170" name="gps_tx" iostandard="LVCMOS33" loc="D9" drive="8" slew="FAST"/>
|
||||||
|
<pin index="171" name="gps_rx" iostandard="LVCMOS33" loc="A9" drive="8" slew="FAST"/>
|
||||||
|
|
||||||
|
<pin index="180" name="SPI_D0" iostandard="LVCMOS33" loc="D11" drive="8" slew="FAST"/>
|
||||||
|
<pin index="181" name="SPI_D1" iostandard="LVCMOS33" loc="E11" drive="8" slew="FAST"/>
|
||||||
|
<pin index="182" name="SPI_FCS" iostandard="LVCMOS33" loc="H11" drive="8" slew="FAST"/>
|
||||||
|
<pin index="183" name="SPI_CCLK" iostandard="LVCMOS33" loc="F10" drive="8" slew="FAST"/>
|
||||||
|
</pins>
|
||||||
|
</part_info>
|
||||||
155
iw-rfsoc-2t2r-47dr/1.0/preset.xml
Normal file
155
iw-rfsoc-2t2r-47dr/1.0/preset.xml
Normal file
@ -0,0 +1,155 @@
|
|||||||
|
<?xml version="1.0" encoding="utf-8"?>
|
||||||
|
|
||||||
|
<ip_presets schema="1.0">
|
||||||
|
<ip_preset preset_proc_name="zynq_ultra_ps_e_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" version="*">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ" value="1200" />
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__BG_ADDR_COUNT" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__CL" value="17"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__CWL" value="12"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__DEVICE_CAPACITY" value="8192 MBits"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__DRAM_WIDTH" value="16 Bits"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__ROW_ADDR_COUNT" value="16"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__SPEED_BIN" value="DDR4_2400R"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__T_RC" value="45.75"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__T_RCD" value="17"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__DDRC__T_RP" value="17"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__ENET3__GRP_MDIO__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__ENET3__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__IO" value="MIO 30 .. 31"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__MODE" value="Dual Parallel"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__SD1__GRP_CD__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__IO" value="MIO 46 .. 51"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__SD1__SLOT_TYPE" value="SD 2.0"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__ENABLE" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__IO" value="MIO 18 .. 19"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
<ip_preset preset_proc_name="pl_ref_clk0_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
<ip_preset preset_proc_name="pl_sysref_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="util_ds_buf">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_BUF_TYPE" value="IBUFDSGTE"/>
|
||||||
|
<user_parameter name="CONFIG.C_SIZE" value="1"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
<ip_preset preset_proc_name="ddr4_clk0_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="util_ds_buf">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_BUF_TYPE" value="IBUFDSGTE"/>
|
||||||
|
<user_parameter name="CONFIG.C_SIZE" value="1"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="300"/>
|
||||||
|
<user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
<ip_preset preset_proc_name="ddr4_sdram_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="ddr4">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C0.DDR4_DataWidth" value="32"/>
|
||||||
|
<user_parameter name="CONFIG.C0.DDR4_InputClockPeriod" value="3334"/>
|
||||||
|
<user_parameter name="CONFIG.C0.DDR4_MemoryPart" value="MT40A256M16LY-062E"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
<ip_preset preset_proc_name="led_8bits_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
|
||||||
|
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
|
||||||
|
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_USE_GPO1" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_GPO1_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_USE_GPO2" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_GPO2_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_USE_GPO3" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_GPO3_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_USE_GPO4" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_GPO4_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.USE_GPO1" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.GPO1_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.USE_GPO2" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.GPO2_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.USE_GPO3" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.GPO3_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.USE_GPO4" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.GPO4_SIZE" value="8"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
<ip_preset preset_proc_name="rs232_uart_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
<ip_preset preset_proc_name="gps_uart_preset">
|
||||||
|
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||||
|
<user_parameters>
|
||||||
|
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||||
|
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||||
|
</user_parameters>
|
||||||
|
</ip>
|
||||||
|
</ip_preset>
|
||||||
|
</ip_presets>
|
||||||
38
iw-rfsoc-2t2r-47dr/1.0/xitem.json
Normal file
38
iw-rfsoc-2t2r-47dr/1.0/xitem.json
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
{
|
||||||
|
"config": {
|
||||||
|
"items": [
|
||||||
|
{
|
||||||
|
"infra": {
|
||||||
|
"name": "iw-rfsoc-2t2r-47dr",
|
||||||
|
"display": "Interwiser RFSoC 2T2R Development Kit (47DR)",
|
||||||
|
"revision": "1.0",
|
||||||
|
"description": "Interwiser RFSoC 2T2R Development Kit (47DR)",
|
||||||
|
"company": "interwiser.com",
|
||||||
|
"company_display": "Interwiser",
|
||||||
|
"author": "Tifer King",
|
||||||
|
"contributors": [
|
||||||
|
{
|
||||||
|
"group": "15inTech",
|
||||||
|
"url": "www.15zk.net"
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"category": "Single Part",
|
||||||
|
"logo": "iw-rfsoc-2t2r-47dr_image.jpg",
|
||||||
|
"website": "https://wiki.15zk.net/zh/boards/IW-RFSOC-2T2R",
|
||||||
|
"search-keywords": [
|
||||||
|
"Interwiser",
|
||||||
|
"interwiser.com",
|
||||||
|
"15inTech",
|
||||||
|
"15zk.net",
|
||||||
|
"rfsoc",
|
||||||
|
"47dr",
|
||||||
|
"2T2R",
|
||||||
|
"Single Part"
|
||||||
|
]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"_major": 1,
|
||||||
|
"_minor": 0
|
||||||
|
}
|
||||||
Loading…
x
Reference in New Issue
Block a user